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author | Andrew Waterman <andrew@sifive.com> | 2023-09-27 15:06:57 -0700 |
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committer | GitHub <noreply@github.com> | 2023-09-27 15:06:57 -0700 |
commit | 847fe5d59a5e198146eca6a3c69fe96b07dad5c6 (patch) | |
tree | a33e0488f380d538ad909d807a069bf6966e3873 | |
parent | 67df25aedc93183ced375e04f87931178b9e9c26 (diff) | |
parent | cf3f787474a590845300f0ac80e6feaf3f58dbdc (diff) | |
download | riscv-isa-sim-847fe5d59a5e198146eca6a3c69fe96b07dad5c6.zip riscv-isa-sim-847fe5d59a5e198146eca6a3c69fe96b07dad5c6.tar.gz riscv-isa-sim-847fe5d59a5e198146eca6a3c69fe96b07dad5c6.tar.bz2 |
Merge pull request #1471 from mehnadnerd/patch-1
Change disasm for vset{i}vli with reserved vtypes to display the reserved bits
-rw-r--r-- | disasm/disasm.cc | 46 |
1 files changed, 27 insertions, 19 deletions
diff --git a/disasm/disasm.cc b/disasm/disasm.cc index b2bed47..15e767e 100644 --- a/disasm/disasm.cc +++ b/disasm/disasm.cc @@ -413,27 +413,35 @@ struct : public arg_t { int lmul = insn.v_lmul(); auto vta = insn.v_vta() == 1 ? "ta" : "tu"; auto vma = insn.v_vma() == 1 ? "ma" : "mu"; - s << "e" << sew; - if(insn.v_frac_lmul()) { - std::string lmul_str = ""; - switch(lmul){ - case 3: - lmul_str = "f2"; - break; - case 2: - lmul_str = "f4"; - break; - case 1: - lmul_str = "f8"; - break; - default: - assert(true && "unsupport fractional LMUL"); - } - s << ", m" << lmul_str; + int newType = (insn.bits() & 0x80000000) ? insn.v_zimm10() : insn.v_zimm11(); + // if bit 31 is set, this is vsetivli and there is a 10-bit vtype, else this is vsetvli and there is an 11-bit vtype + // If the provided vtype has reserved bits, display the hex version of the vtype instead + if ((newType >> 8) != 0) { + s << "0x" << std::hex << newType; } else { - s << ", m" << (1 << lmul); + s << "e" << sew; + if(insn.v_frac_lmul()) { + std::string lmul_str = ""; + switch(lmul){ + case 3: + lmul_str = "f2"; + break; + case 2: + lmul_str = "f4"; + break; + case 1: + lmul_str = "f8"; + break; + default: + assert(true && "unsupport fractional LMUL"); + } + s << ", m" << lmul_str; + } else { + s << ", m" << (1 << lmul); + } + s << ", " << vta << ", " << vma; } - s << ", " << vta << ", " << vma; + return s.str(); } } v_vtype; |