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| author | YenHaoChen <howard25336284@gmail.com> | 2023-07-26 08:35:37 +0800 |
|---|---|---|
| committer | YenHaoChen <howard25336284@gmail.com> | 2023-07-26 08:54:09 +0800 |
| commit | 63379810b4d5c469de3ba1a9aeb90a8387df8543 (patch) | |
| tree | 630631f7b74d102c903f26d30cda038164ff7798 | |
| parent | 60c08b1ea5e3d96a97c235db87d472a7cfb2611b (diff) | |
| download | riscv-isa-sim-63379810b4d5c469de3ba1a9aeb90a8387df8543.zip riscv-isa-sim-63379810b4d5c469de3ba1a9aeb90a8387df8543.tar.gz riscv-isa-sim-63379810b4d5c469de3ba1a9aeb90a8387df8543.tar.bz2 | |
triggers: fix textra.sbytemask
Ignore corresponding bytes to the scontext and textra.svalue.
Cast 0xff to reg_t for the 34-bit textra64.svalue.
| -rw-r--r-- | riscv/triggers.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/triggers.cc b/riscv/triggers.cc index 39a7330..b2b815d 100644 --- a/riscv/triggers.cc +++ b/riscv/triggers.cc @@ -84,7 +84,7 @@ bool trigger_t::textra_match(processor_t * const proc) const noexcept assert(CSR_TEXTRA32_SBYTEMASK_LENGTH < CSR_TEXTRA64_SBYTEMASK_LENGTH); for (int i = 0; i < CSR_TEXTRA64_SBYTEMASK_LENGTH; i++) if (sbytemask & (1 << i)) - mask &= 0xff << (i * 8); + mask &= ~(reg_t(0xff) << (i * 8)); if ((state->scontext->read() & mask) != (svalue & mask)) return false; } else if (sselect == SSELECT_ASID) { |