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| author | Andrew Waterman <andrew@sifive.com> | 2023-07-20 20:47:12 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-07-20 20:47:12 -0700 |
| commit | 5e375b98d9a8aeddbeb4befe7a569b88c80ef037 (patch) | |
| tree | 9fbd7d7393ec09b5eca5df298608c560848e9248 | |
| parent | 1b41ed3c48b5425b6d35a54043ae422789fca473 (diff) | |
| parent | 6bfab0e212b381953a5c8b6cc6e8bd1dbed56ec8 (diff) | |
| download | riscv-isa-sim-5e375b98d9a8aeddbeb4befe7a569b88c80ef037.zip riscv-isa-sim-5e375b98d9a8aeddbeb4befe7a569b88c80ef037.tar.gz riscv-isa-sim-5e375b98d9a8aeddbeb4befe7a569b88c80ef037.tar.bz2 | |
Merge pull request #1422 from mbgg/fix-prefix-warning
Fix compilation warning in riscv/execute.cc
| -rw-r--r-- | riscv/execute.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/execute.cc b/riscv/execute.cc index 295879d..591090b 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -85,7 +85,7 @@ static void commit_log_print_insn(processor_t *p, reg_t pc, insn_t insn) if (item.first == 0) continue; - char prefix; + char prefix = ' '; int size; int rd = item.first >> 4; bool is_vec = false; |