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| author | YenHaoChen <howard25336284@gmail.com> | 2023-07-13 10:57:32 +0800 |
|---|---|---|
| committer | YenHaoChen <howard25336284@gmail.com> | 2023-07-13 12:04:09 +0800 |
| commit | 4aea5a05ad7bf1b48b2d87e000e6575f68747033 (patch) | |
| tree | 597ac084c445bad6b40d879d6f62e9533dea8d52 | |
| parent | faceda27e60c0721b3233658198bcf50d09b02cc (diff) | |
| download | riscv-isa-sim-4aea5a05ad7bf1b48b2d87e000e6575f68747033.zip riscv-isa-sim-4aea5a05ad7bf1b48b2d87e000e6575f68747033.tar.gz riscv-isa-sim-4aea5a05ad7bf1b48b2d87e000e6575f68747033.tar.bz2 | |
fix mcontrol's tval on cbo_zero
The tval should capture the effective address on an (trigger) exception.
Reference: https://github.com/riscv/riscv-CMOs/issues/55
| -rw-r--r-- | riscv/mmu.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/riscv/mmu.h b/riscv/mmu.h index 62e9a73..cfbe57c 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -219,8 +219,10 @@ public: void cbo_zero(reg_t addr) { auto base = addr & ~(blocksz - 1); - for (size_t offset = 0; offset < blocksz; offset += 1) + for (size_t offset = 0; offset < blocksz; offset += 1) { + check_triggers(triggers::OPERATION_STORE, base + offset, false, addr, std::nullopt); store<uint8_t>(base + offset, 0); + } } void clean_inval(reg_t addr, bool clean, bool inval) { |