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| author | Andrew Waterman <andrew@sifive.com> | 2023-07-19 14:07:14 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-07-19 14:07:14 -0700 |
| commit | 432c9ee97613ec73bbb10591f0cef9c1c93b4284 (patch) | |
| tree | 2ebe5236afaca83374f5fadf846c2effc0d2e070 | |
| parent | 371353288e0c6a94713309c5400548f178648b7a (diff) | |
| parent | 8658429647eb6952707e2bf2a3bb4eca75a8e379 (diff) | |
| download | riscv-isa-sim-432c9ee97613ec73bbb10591f0cef9c1c93b4284.zip riscv-isa-sim-432c9ee97613ec73bbb10591f0cef9c1c93b4284.tar.gz riscv-isa-sim-432c9ee97613ec73bbb10591f0cef9c1c93b4284.tar.bz2 | |
Merge pull request #1413 from YenHaoChen/pr-mcontrol-cbo-zero-tval
mcontrol/mcontrol6 on CBO
| -rw-r--r-- | riscv/mmu.cc | 6 | ||||
| -rw-r--r-- | riscv/mmu.h | 12 |
2 files changed, 13 insertions, 5 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index 3f90060..f6d23a3 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -169,7 +169,7 @@ bool mmu_t::mmio(reg_t paddr, size_t len, uint8_t* bytes, access_type type) return true; } -void mmu_t::check_triggers(triggers::operation_t operation, reg_t address, bool virt, std::optional<reg_t> data) +void mmu_t::check_triggers(triggers::operation_t operation, reg_t address, bool virt, reg_t tval, std::optional<reg_t> data) { if (matched_trigger || !proc) return; @@ -179,13 +179,13 @@ void mmu_t::check_triggers(triggers::operation_t operation, reg_t address, bool if (match.has_value()) switch (match->timing) { case triggers::TIMING_BEFORE: - throw triggers::matched_t(operation, address, match->action, virt); + throw triggers::matched_t(operation, tval, match->action, virt); case triggers::TIMING_AFTER: // We want to take this exception on the next instruction. We check // whether to do so in the I$ refill path, so flush the I$. flush_icache(); - matched_trigger = new triggers::matched_t(operation, address, match->action, virt); + matched_trigger = new triggers::matched_t(operation, tval, match->action, virt); } } diff --git a/riscv/mmu.h b/riscv/mmu.h index 8c2bdbe..ce50527 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -219,11 +219,16 @@ public: void cbo_zero(reg_t addr) { auto base = addr & ~(blocksz - 1); - for (size_t offset = 0; offset < blocksz; offset += 1) + for (size_t offset = 0; offset < blocksz; offset += 1) { + check_triggers(triggers::OPERATION_STORE, base + offset, false, addr, std::nullopt); store<uint8_t>(base + offset, 0); + } } void clean_inval(reg_t addr, bool clean, bool inval) { + auto base = addr & ~(blocksz - 1); + for (size_t offset = 0; offset < blocksz; offset += 1) + check_triggers(triggers::OPERATION_STORE, base + offset, false, addr, std::nullopt); convert_load_traps_to_store_traps({ const reg_t paddr = translate(generate_access_info(addr, LOAD, {false, false, false}), 1); if (sim->reservable(paddr)) { @@ -402,7 +407,10 @@ private: bool mmio_store(reg_t paddr, size_t len, const uint8_t* bytes); bool mmio(reg_t paddr, size_t len, uint8_t* bytes, access_type type); bool mmio_ok(reg_t paddr, access_type type); - void check_triggers(triggers::operation_t operation, reg_t address, bool virt, std::optional<reg_t> data = std::nullopt); + void check_triggers(triggers::operation_t operation, reg_t address, bool virt, std::optional<reg_t> data = std::nullopt) { + check_triggers(operation, address, virt, address, data); + } + void check_triggers(triggers::operation_t operation, reg_t address, bool virt, reg_t tval, std::optional<reg_t> data); reg_t translate(mem_access_info_t access_info, reg_t len); reg_t pte_load(reg_t pte_paddr, reg_t addr, bool virt, access_type trap_type, size_t ptesize) { |