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| author | brs <turtwig@utexas.edu> | 2023-10-19 10:55:40 -0500 |
|---|---|---|
| committer | brs <turtwig@utexas.edu> | 2023-10-19 10:55:40 -0500 |
| commit | 177ecae3656acc8d66d0c50687cd92fad169e8cd (patch) | |
| tree | 2c22a3c4cf45327d4138896374bd7f74efec2b4a | |
| parent | 9258b59e67f92332fe057e4856e3e2f07312bfe5 (diff) | |
| download | riscv-isa-sim-177ecae3656acc8d66d0c50687cd92fad169e8cd.zip riscv-isa-sim-177ecae3656acc8d66d0c50687cd92fad169e8cd.tar.gz riscv-isa-sim-177ecae3656acc8d66d0c50687cd92fad169e8cd.tar.bz2 | |
Update to Zalasr encodings to require the aq/rl bits be set rather than assuming they are
| -rw-r--r-- | riscv/encoding.h | 34 |
1 files changed, 17 insertions, 17 deletions
diff --git a/riscv/encoding.h b/riscv/encoding.h index 1a0f554..7ee3e3d 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -4,7 +4,7 @@ /* * This file is auto-generated by running 'make' in - * https://github.com/riscv/riscv-opcodes (4f28129) + * https://github.com/riscv/riscv-opcodes (65c40e9) */ #ifndef RISCV_CSR_ENCODING_H @@ -1386,20 +1386,20 @@ #define MASK_KWMMUL_U 0xfe00707f #define MATCH_LB 0x3 #define MASK_LB 0x707f -#define MATCH_LB_AQ 0x3000002f -#define MASK_LB_AQ 0xf9f0707f +#define MATCH_LB_AQ 0x3400002f +#define MASK_LB_AQ 0xfdf0707f #define MATCH_LBU 0x4003 #define MASK_LBU 0x707f #define MATCH_LD 0x3003 #define MASK_LD 0x707f -#define MATCH_LD_AQ 0x3000302f -#define MASK_LD_AQ 0xf9f0707f +#define MATCH_LD_AQ 0x3400302f +#define MASK_LD_AQ 0xfdf0707f #define MATCH_LDU 0x7003 #define MASK_LDU 0x707f #define MATCH_LH 0x1003 #define MASK_LH 0x707f -#define MATCH_LH_AQ 0x3000102f -#define MASK_LH_AQ 0xf9f0707f +#define MATCH_LH_AQ 0x3400102f +#define MASK_LH_AQ 0xfdf0707f #define MATCH_LHU 0x5003 #define MASK_LHU 0x707f #define MATCH_LQ 0x300f @@ -1412,8 +1412,8 @@ #define MASK_LUI 0x7f #define MATCH_LW 0x2003 #define MASK_LW 0x707f -#define MATCH_LW_AQ 0x3000202f -#define MASK_LW_AQ 0xf9f0707f +#define MATCH_LW_AQ 0x3400202f +#define MASK_LW_AQ 0xfdf0707f #define MATCH_LWU 0x6003 #define MASK_LWU 0x707f #define MATCH_MADDR32 0xc4001077 @@ -1628,8 +1628,8 @@ #define MASK_RSUBW 0xfe00707f #define MATCH_SB 0x23 #define MASK_SB 0x707f -#define MATCH_SB_RL 0x3800002f -#define MASK_SB_RL 0xf8007fff +#define MATCH_SB_RL 0x3a00002f +#define MASK_SB_RL 0xfa007fff #define MATCH_SC_D 0x1800302f #define MASK_SC_D 0xf800707f #define MATCH_SC_W 0x1800202f @@ -1650,8 +1650,8 @@ #define MASK_SCMPLT8 0xfe00707f #define MATCH_SD 0x3023 #define MASK_SD 0x707f -#define MATCH_SD_RL 0x3800302f -#define MASK_SD_RL 0xf8007fff +#define MATCH_SD_RL 0x3a00302f +#define MASK_SD_RL 0xfa007fff #define MATCH_SEXT_B 0x60401013 #define MASK_SEXT_B 0xfff0707f #define MATCH_SEXT_H 0x60501013 @@ -1676,8 +1676,8 @@ #define MASK_SH3ADD 0xfe00707f #define MATCH_SH3ADD_UW 0x2000603b #define MASK_SH3ADD_UW 0xfe00707f -#define MATCH_SH_RL 0x3800102f -#define MASK_SH_RL 0xf8007fff +#define MATCH_SH_RL 0x3a00102f +#define MASK_SH_RL 0xfa007fff #define MATCH_SHA256SIG0 0x10201013 #define MASK_SHA256SIG0 0xfff0707f #define MATCH_SHA256SIG1 0x10301013 @@ -1984,8 +1984,8 @@ #define MASK_SUNPKD832 0xfff0707f #define MATCH_SW 0x2023 #define MASK_SW 0x707f -#define MATCH_SW_RL 0x3800202f -#define MASK_SW_RL 0xf8007fff +#define MATCH_SW_RL 0x3a00202f +#define MASK_SW_RL 0xfa007fff #define MATCH_UCLIP16 0x85000077 #define MASK_UCLIP16 0xff00707f #define MATCH_UCLIP32 0xf4000077 |