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authorAndrew Waterman <aswaterman@gmail.com>2018-08-17 18:49:47 -0700
committerGitHub <noreply@github.com>2018-08-17 18:49:47 -0700
commit8a485de092c1ffc79105db34aca8875203921d63 (patch)
tree882b1837431d8bfb37d409b980200b9d4072d54e
parentbed0a54fdaedf09a4c6523a2a116b59d021fb12b (diff)
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Don't increment instret immediately after it is written (#231)
This brings Spike into compliance with this clause in the spec: https://github.com/riscv/riscv-isa-manual/blob/master/src/csr.tex#L96
-rw-r--r--riscv/processor.cc6
1 files changed, 6 insertions, 0 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc
index 2a4a18c..ecbe3ef 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -403,10 +403,16 @@ void processor_t::set_csr(int which, reg_t val)
state.minstret = (state.minstret >> 32 << 32) | (val & 0xffffffffU);
else
state.minstret = val;
+ // The ISA mandates that if an instruction writes instret, the write
+ // takes precedence over the increment to instret. However, Spike
+ // unconditionally increments instret after executing an instruction.
+ // Correct for this artifact by decrementing instret here.
+ state.minstret--;
break;
case CSR_MINSTRETH:
case CSR_MCYCLEH:
state.minstret = (val << 32) | (state.minstret << 32 >> 32);
+ state.minstret--; // See comment above.
break;
case CSR_SCOUNTEREN:
state.scounteren = val;