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| author | Tim Newsome <tim@sifive.com> | 2017-09-21 14:54:06 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2017-09-21 14:54:06 -0700 |
| commit | def8b3e05d754c8115deb0c8b8c91dc4e33975fd (patch) | |
| tree | 16744923a356a6e2ca3f399562000394538a5cc6 | |
| parent | 526d3997e68200ef3f372384acdc13e8e8b92e31 (diff) | |
| download | riscv-isa-sim-def8b3e05d754c8115deb0c8b8c91dc4e33975fd.zip riscv-isa-sim-def8b3e05d754c8115deb0c8b8c91dc4e33975fd.tar.gz riscv-isa-sim-def8b3e05d754c8115deb0c8b8c91dc4e33975fd.tar.bz2 | |
Actually let hartreset be set.
| -rw-r--r-- | riscv/debug_module.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc index 8d73f07..985cbbd 100644 --- a/riscv/debug_module.cc +++ b/riscv/debug_module.cc @@ -447,6 +447,7 @@ bool debug_module_t::dmi_write(unsigned address, uint32_t value) if (dmcontrol.dmactive) { dmcontrol.haltreq = get_field(value, DMI_DMCONTROL_HALTREQ); dmcontrol.resumereq = get_field(value, DMI_DMCONTROL_RESUMEREQ); + dmcontrol.hartreset = get_field(value, DMI_DMCONTROL_HARTRESET); dmcontrol.ndmreset = get_field(value, DMI_DMCONTROL_NDMRESET); dmcontrol.hartsel = get_field(value, DMI_DMCONTROL_HARTSEL); } else { |