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rocket-tools/riscv-gnu-toolchain/spike.git
confprec
cs250
cycleh
debug_rom
debug_rom_fence
device_flags
dtm_reset_error
dts_parsing
dynamic
eos18-bringup
factor-out-macros
fix-bf16
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fp-encoding
heterogeneous_mc
hwachav4
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itrigger-etrigger-cleanup
load_reservation_set_size
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no_progbuf2
nolibfdt
p-ext-0.5.2
plctlab-plct-zce-fix2
plic-clint-endian
plic_uart_v1
priv-1.10
private-l1-caches
pte-info-and-delegation
remove-tests
rivosinc-etrigger_fix_exception_match
rva-profile-support
simplify-misaligned
sodor
sparse-mem
speedup-hacks
static-link
test
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tweak_debug_rom
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path:
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/
riscv
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insns
/
srl.h
blob: 0dabe9ecde160c95c58e72248cd78b22918d5d3d (
plain
)
1
WRITE_RD
(
sext_xlen
(
zext_xlen
(
RS1
) >> (
RS2
& (
xlen
-
1
))));