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rocket-tools/riscv-gnu-toolchain/spike.git
confprec
cs250
cycleh
debug_rom
debug_rom_fence
device_flags
dtm_reset_error
dts_parsing
dynamic
eos18-bringup
factor-out-macros
fix-bf16
fix-cfg-priv
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fp-encoding
heterogeneous_mc
hwachav4
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itrigger-etrigger-cleanup
load_reservation_set_size
log-commits-faster
master
mmio-hack
mvp
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no_progbuf2
nolibfdt
p-ext-0.5.2
plctlab-plct-zce-fix2
plic-clint-endian
plic_uart_v1
priv-1.10
private-l1-caches
pte-info-and-delegation
remove-tests
rivosinc-etrigger_fix_exception_match
rva-profile-support
simplify-misaligned
sodor
sparse-mem
speedup-hacks
static-link
test
tmp
trigger_priority
tweak_debug_rom
whole-archive
sifive/rvv0.9-phase2
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path:
root
/
riscv
/
insns
/
c_sh.h
blob: 271ca09db65aaa389837f742e345d464fa4df3bc (
plain
)
1
2
require_extension
(
EXT_ZCB
);
MMU
.
store
<
uint16_t
>(
RVC_RS1S
+
insn
.
rvc_lhimm
(),
RVC_RS2S
);