1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
|
// See LICENSE for license details.
#include "processor.h"
#include "mmu.h"
#include <cassert>
static void commit_log_stash_privilege(state_t* state)
{
#ifdef RISCV_ENABLE_COMMITLOG
state->last_inst_priv = state->prv;
#endif
}
static void commit_log_print_insn(state_t* state, reg_t pc, insn_t insn)
{
#ifdef RISCV_ENABLE_COMMITLOG
int32_t priv = state->last_inst_priv;
uint64_t mask = (insn.length() == 8 ? uint64_t(0) : (uint64_t(1) << (insn.length() * 8))) - 1;
if (state->log_reg_write.addr) {
fprintf(stderr, "%1d 0x%016" PRIx64 " (0x%08" PRIx64 ") %c%2" PRIu64 " 0x%016" PRIx64 "\n",
priv,
pc,
insn.bits() & mask,
state->log_reg_write.addr & 1 ? 'f' : 'x',
state->log_reg_write.addr >> 1,
state->log_reg_write.data);
} else {
fprintf(stderr, "%1d 0x%016" PRIx64 " (0x%08" PRIx64 ")\n", priv, pc, insn.bits() & mask);
}
state->log_reg_write.addr = 0;
#endif
}
inline void processor_t::update_histogram(reg_t pc)
{
#ifdef RISCV_ENABLE_HISTOGRAM
pc_histogram[pc]++;
#endif
}
static reg_t execute_insn(processor_t* p, reg_t pc, insn_fetch_t fetch)
{
commit_log_stash_privilege(p->get_state());
reg_t npc = fetch.func(p, fetch.insn, pc);
if (!invalid_pc(npc)) {
commit_log_print_insn(p->get_state(), pc, fetch.insn);
p->update_histogram(pc);
}
return npc;
}
// fetch/decode/execute loop
void processor_t::step(size_t n)
{
// TODO: We should really not call this function at all when halted, to avoid
// burning CPU.
if (single_step) {
set_halted(false, HR_NONE);
n = 1;
}
while (run && !halted && n > 0) {
size_t instret = 0;
reg_t pc = state.pc;
mmu_t* _mmu = mmu;
#define advance_pc() \
if (unlikely(invalid_pc(pc))) { \
switch (pc) { \
case PC_SERIALIZE_BEFORE: state.serialized = true; break; \
case PC_SERIALIZE_AFTER: instret++; break; \
default: abort(); \
} \
pc = state.pc; \
break; \
} else { \
state.pc = pc; \
instret++; \
}
try
{
take_interrupt();
if (unlikely(debug))
{
while (instret < n)
{
insn_fetch_t fetch = mmu->load_insn(pc);
if (!state.serialized)
disasm(fetch.insn);
pc = execute_insn(this, pc, fetch);
advance_pc();
}
}
else while (instret < n)
{
size_t idx = _mmu->icache_index(pc);
auto ic_entry = _mmu->access_icache(pc);
#define ICACHE_ACCESS(i) { \
insn_fetch_t fetch = ic_entry->data; \
ic_entry++; \
pc = execute_insn(this, pc, fetch); \
if (i == mmu_t::ICACHE_ENTRIES-1) break; \
if (unlikely(ic_entry->tag != pc)) goto miss; \
if (unlikely(instret+1 == n)) break; \
instret++; \
state.pc = pc; \
}
switch (idx) {
#include "icache.h"
}
advance_pc();
continue;
miss:
advance_pc();
// refill I$ if it looks like there wasn't a taken branch
if (pc > (ic_entry-1)->tag && pc <= (ic_entry-1)->tag + MAX_INSN_LENGTH)
_mmu->refill_icache(pc, ic_entry);
}
}
catch(trap_t& t)
{
take_trap(t, pc);
n = instret;
}
state.minstret += instret;
n -= instret;
}
if (single_step) {
single_step = false;
set_halted(true, HR_STEPPED);
}
}
|