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2020-05-19fdt: import fdt library from OpenSBIChih-Min Chao1-0/+1
2020-05-18rvv: disasm: add missing .wx formatChih-Min Chao1-1/+3
2020-05-18rvv: disasm: fix unorder index storeChih-Min Chao1-1/+1
2020-05-14rvv: disasm: fix amo formatChih-Min Chao1-1/+1
2020-05-14disasm: refine structure nameChih-Min Chao1-3/+3
2020-05-14rvv: add lmul=1 (m0) in disasm messageDave.Wen1-19/+17
2020-05-14rvv: fix the fractional lmulDave.Wen1-3/+3
2020-05-13rvv: change to 0.9amoChih-Min Chao1-19/+36
2020-05-13rvv: amo pre-0.9Chih-Min Chao1-0/+27
2020-05-13rvv: fractional_lmul when lmul < 1Dave.Wen1-2/+22
2020-05-13vtype: fix the vta and vma functions and debugging displayDave.Wen1-0/+3
2020-05-12rvv: add ext opcodeChih-Min Chao1-0/+8
2020-05-12rvv: op: change vfunary0 and funary1 func6 fieldChih-Min Chao1-3/+9
2020-05-11rvv: change to 0.9 ldstChih-Min Chao1-65/+58
2020-05-04zfh: add fp16 disasmChih-Min Chao1-0/+38
2020-04-16rvv: fix rtz cvtChih-Min Chao1-2/+2
2020-04-14rvv: disasm: leave only SEW-bit segment load/storeChih-Min Chao1-66/+0
2020-04-14rvv: add vfslide1[down|up].vf and refine checking ruleChih-Min Chao1-0/+2
2020-04-14rvv: add float conversion for rtz variantsChih-Min Chao1-1/+7
2020-04-14Handle misaligned memories by aligning them, rather than erroringAndrew Waterman1-1/+16
2020-04-14Revert "rvv: support simulations with mem size <4K"Chih-Min Chao1-1/+1
2020-04-07rvv: support simulations with mem size <4KDave.Wen1-1/+1
2020-04-05Write execution logs to a named log file (#409)Rupert Swarbrick2-5/+8
2020-03-04rvv: remove the option of vector misaligned accessZhen Wei1-3/+0
2020-03-04rvv: remove the option of vector impl. checkZhen Wei1-32/+0
2020-02-19Add optional support for real-time clintAnup Patel1-1/+5
2020-02-19Make spike capable of booting LinuxAnup Patel1-1/+39
2020-02-12Fix immediate signedness in vector disassemblyAndrew Waterman1-3/+3
2020-02-12Decouple spike-dasm program from simulator codeAndrew Waterman1-4/+21
2020-01-06rvv : vmv[1248]r.vChih-Min Chao1-4/+9
2019-12-12rvv: fix vfwcvt/vfncvt for f32 -> f64 and f64 -> f32Chih-Min Chao1-11/+9
2019-11-27rvv: add whole register load/store, vl1r.v/vs1r.vChih-Min Chao1-11/+11
2019-11-27rvv: replace vn suffic by 'w'Chih-Min Chao1-26/+30
2019-11-27rvv: add load/store whole registerChih-Min Chao1-0/+4
2019-11-27rvv: rename vfncvt suffix and add rod rouding typeChih-Min Chao1-15/+21
2019-11-27rvv: add quad insn and new vlenb csrChih-Min Chao1-5/+5
2019-11-17add vaaddu/vasubu/vfncvt.rod.f.f.v to diassemblerAndrew Waterman1-2/+5
2019-11-17Add --priv option to control which privilege modes are availableAndrew Waterman3-3/+6
2019-10-22rvv: remove vmfordChih-Min Chao1-1/+0
2019-10-14rvv: update encoding to v0.8Chih-Min Chao1-1/+1
2019-10-08Speed up compilation of disasm.cc, especially in clangAndrew Waterman1-1/+1
2019-09-29Adds --log-commits commandline option. (#323)dave-estes-syzexion1-0/+3
2019-09-05rvv: change vext to vmvChih-Min Chao1-1/+1
2019-09-05Revert "vext.x.v -> vmv.x.s; unary operation encoding changes"Chih-Min Chao1-1/+1
2019-09-04rvv: refine check logic to use string as inputChih-Min Chao1-2/+14
2019-09-04rvv: exit when there is unsupported instructionsChih-Min Chao1-0/+11
2019-09-04rvv: reimplement check-1905 as check-implChih-Min Chao1-2/+9
2019-09-04Implement MMIO device plugins.Aaron Jones1-3/+64
2019-09-04Fix c.fldsp/c.fsdsp disassembly bugAndrew Waterman1-2/+2
2019-09-04vext.x.v -> vmv.x.s; unary operation encoding changesAndrew Waterman1-1/+1