rocket-tools/riscv-gnu-toolchain/spike.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2020-05-22	rvv: disasm: fix vsetvli	Chih-Min Chao	1	-1/+1
2020-05-19	fdt: restructure dtb create and config flow	Chih-Min Chao	1	-3/+1
2020-05-19	fdt: option: add --dtb option to specify dtb binary file	Chih-Min Chao	1	-0/+3
2020-05-19	fdt: import fdt library from OpenSBI	Chih-Min Chao	1	-0/+1
2020-05-18	rvv: disasm: add missing .wx format	Chih-Min Chao	1	-1/+3
2020-05-18	rvv: disasm: fix unorder index store	Chih-Min Chao	1	-1/+1
2020-05-14	rvv: disasm: fix amo format	Chih-Min Chao	1	-1/+1
2020-05-14	disasm: refine structure name	Chih-Min Chao	1	-3/+3
2020-05-14	rvv: add lmul=1 (m0) in disasm message	Dave.Wen	1	-19/+17
2020-05-14	rvv: fix the fractional lmul	Dave.Wen	1	-3/+3
2020-05-13	rvv: change to 0.9amo	Chih-Min Chao	1	-19/+36
2020-05-13	rvv: amo pre-0.9	Chih-Min Chao	1	-0/+27
2020-05-13	rvv: fractional_lmul when lmul < 1	Dave.Wen	1	-2/+22
2020-05-13	vtype: fix the vta and vma functions and debugging display	Dave.Wen	1	-0/+3
2020-05-12	rvv: add ext opcode	Chih-Min Chao	1	-0/+8
2020-05-12	rvv: op: change vfunary0 and funary1 func6 field	Chih-Min Chao	1	-3/+9
2020-05-11	rvv: change to 0.9 ldst	Chih-Min Chao	1	-65/+58
2020-05-04	zfh: add fp16 disasm	Chih-Min Chao	1	-0/+38
2020-04-16	rvv: fix rtz cvt	Chih-Min Chao	1	-2/+2
2020-04-14	rvv: disasm: leave only SEW-bit segment load/store	Chih-Min Chao	1	-66/+0
2020-04-14	rvv: add vfslide1[down\|up].vf and refine checking rule	Chih-Min Chao	1	-0/+2
2020-04-14	rvv: add float conversion for rtz variants	Chih-Min Chao	1	-1/+7
2020-04-14	Handle misaligned memories by aligning them, rather than erroring	Andrew Waterman	1	-1/+16
2020-04-14	Revert "rvv: support simulations with mem size <4K"	Chih-Min Chao	1	-1/+1
2020-04-07	rvv: support simulations with mem size <4K	Dave.Wen	1	-1/+1
2020-04-05	Write execution logs to a named log file (#409)	Rupert Swarbrick	2	-5/+8
2020-03-04	rvv: remove the option of vector misaligned access	Zhen Wei	1	-3/+0
2020-03-04	rvv: remove the option of vector impl. check	Zhen Wei	1	-32/+0
2020-02-19	Add optional support for real-time clint	Anup Patel	1	-1/+5
2020-02-19	Make spike capable of booting Linux	Anup Patel	1	-1/+39
2020-02-12	Fix immediate signedness in vector disassembly	Andrew Waterman	1	-3/+3
2020-02-12	Decouple spike-dasm program from simulator code	Andrew Waterman	1	-4/+21
2020-01-06	rvv : vmv[1248]r.v	Chih-Min Chao	1	-4/+9
2019-12-12	rvv: fix vfwcvt/vfncvt for f32 -> f64 and f64 -> f32	Chih-Min Chao	1	-11/+9
2019-11-27	rvv: add whole register load/store, vl1r.v/vs1r.v	Chih-Min Chao	1	-11/+11
2019-11-27	rvv: replace vn suffic by 'w'	Chih-Min Chao	1	-26/+30
2019-11-27	rvv: add load/store whole register	Chih-Min Chao	1	-0/+4
2019-11-27	rvv: rename vfncvt suffix and add rod rouding type	Chih-Min Chao	1	-15/+21
2019-11-27	rvv: add quad insn and new vlenb csr	Chih-Min Chao	1	-5/+5
2019-11-17	add vaaddu/vasubu/vfncvt.rod.f.f.v to diassembler	Andrew Waterman	1	-2/+5
2019-11-17	Add --priv option to control which privilege modes are available	Andrew Waterman	3	-3/+6
2019-10-22	rvv: remove vmford	Chih-Min Chao	1	-1/+0
2019-10-14	rvv: update encoding to v0.8	Chih-Min Chao	1	-1/+1
2019-10-08	Speed up compilation of disasm.cc, especially in clang	Andrew Waterman	1	-1/+1
2019-09-29	Adds --log-commits commandline option. (#323)	dave-estes-syzexion	1	-0/+3
2019-09-05	rvv: change vext to vmv	Chih-Min Chao	1	-1/+1
2019-09-05	Revert "vext.x.v -> vmv.x.s; unary operation encoding changes"	Chih-Min Chao	1	-1/+1
2019-09-04	rvv: refine check logic to use string as input	Chih-Min Chao	1	-2/+14
2019-09-04	rvv: exit when there is unsupported instructions	Chih-Min Chao	1	-0/+11
2019-09-04	rvv: reimplement check-1905 as check-impl	Chih-Min Chao	1	-2/+9