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disasm.cc
Age
Commit message (
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Author
Files
Lines
2020-07-29
rvv: add vrgatherei16.vv
Chih-Min Chao
1
-13
/
+14
2020-07-29
rvv: add new whole reg load/store instructions
Chih-Min Chao
1
-2
/
+25
2020-07-29
rvv: op: fix amo naming
Chih-Min Chao
1
-4
/
+4
2020-07-29
rvv: disasm: fix missing vamoorei operands
Chih-Min Chao
1
-1
/
+2
2020-07-21
Remove deprecated decoding of xor x0,x0,x0
Andrew Waterman
1
-1
/
+0
2020-06-16
Merge pull request #490 from chihminchao/rvv-fix-2020-06-17
Andrew Waterman
1
-1
/
+1
2020-06-16
rvv: disasm: fix vwadd.wx operand
Chih-Min Chao
1
-1
/
+1
2020-06-16
zfh: disasm: add fp16 disasm
Chih-Min Chao
1
-0
/
+38
2020-06-11
rvv: disasm: fix vfncvt.f.f.w
Chih-Min Chao
1
-1
/
+1
2020-05-28
rvv: add new explicit eew load/store instructions
Chih-Min Chao
1
-64
/
+51
2020-05-28
rvv: add amo instructions
Chih-Min Chao
1
-0
/
+50
2020-05-28
rvv: add new singed/unsiged extension instructions
Chih-Min Chao
1
-0
/
+8
2020-05-28
rvv: extenc VU structure to support 0.9 new fields
Chih-Min Chao
1
-2
/
+23
2020-05-28
rvv: op: change funary op
Chih-Min Chao
1
-3
/
+9
2020-05-28
rvv: disasm: add missing .wx format
Chih-Min Chao
1
-1
/
+3
2020-05-04
rvv: fp16: support conversion instrucitons
Chih-Min Chao
1
-2
/
+2
2020-04-24
rvv: disasm: leave only SEW-bit segment load/store
Chih-Min Chao
1
-66
/
+0
2020-04-24
rvv: add vfslide1[down|up].vf and refine checking rule
Chih-Min Chao
1
-0
/
+2
2020-04-20
rvv: add float conversion for rtz variants
Chih-Min Chao
1
-1
/
+7
2020-02-05
Fix immediate signedness in vector disassembly
Andrew Waterman
1
-3
/
+3
2020-01-13
rvv: add vmv[1248]r.v
Chih-Min Chao
1
-4
/
+9
2020-01-13
rvv: fix vfwcvt/vfncvt for f32 -> f64 and f64 -> f32
Chih-Min Chao
1
-11
/
+9
2019-12-20
rvv: replace vn suffic by 'w'
Chih-Min Chao
1
-26
/
+30
2019-12-20
rvv: add load/store whole register instructions
Chih-Min Chao
1
-11
/
+15
2019-12-20
rvv: rename vfncvt suffix and add rod rouding type
Chih-Min Chao
1
-15
/
+21
2019-12-20
rvv: add quad insn and new vlenb csr
Chih-Min Chao
1
-5
/
+5
2019-11-15
add vaaddu/vasubu/vfncvt.rod.f.f.v to diassembler
Andrew Waterman
1
-2
/
+5
2019-10-29
rvv: remove vmford
Chih-Min Chao
1
-1
/
+0
2019-10-07
Speed up compilation of disasm.cc, especially in clang
Andrew Waterman
1
-1
/
+1
2019-08-23
Fix c.fldsp/c.fsdsp disassembly bug
Andrew Waterman
1
-2
/
+2
2019-07-19
vext.x.v -> vmv.x.s; unary operation encoding changes
Andrew Waterman
1
-1
/
+1
2019-07-05
vmfirst/vmpopc have been renamed to vfirst/vpopc
Andrew Waterman
1
-2
/
+2
2019-06-14
rvv: disasm: add v-spec 0.7.1 support
Chih-Min Chao
1
-0
/
+517
2018-10-03
fix disassembly of c.addi4spn
Andrew Waterman
1
-1
/
+1
2018-08-23
Fix several disassembler bugs
Andrew Waterman
1
-57
/
+88
2018-01-03
Add some missing RVC instructions to disassembler
Andrew Waterman
1
-0
/
+3
2017-11-06
Implement Q extension for disassembler (#153)
Kito Cheng
1
-0
/
+36
2017-11-03
Fix disassembly of c.li 0
Andrew Waterman
1
-1
/
+1
2017-08-10
Correct c.li and c.lui disassembly (#118)
Palmer Dabbelt
1
-2
/
+2
2017-04-25
FMV.X.S/FMV.S.X -> FMV.X.W/FMV.W.X
Andrew Waterman
1
-2
/
+2
2017-04-25
Remove hret instruction
Andrew Waterman
1
-1
/
+0
2016-06-29
Disassemble RVC instructions based on XLEN
Andrew Waterman
1
-8
/
+18
2016-06-03
Minor usability improvements (#48)
neuschaefer
1
-1
/
+6
2016-04-28
Remove MTIME[CMP]; add RTC device
Andrew Waterman
1
-1
/
+0
2016-04-19
Split ERET into URET, SRET, HRET, MRET
Andrew Waterman
1
-3
/
+6
2015-10-20
Update to hopefully final RVC 1.9 encoding
Andrew Waterman
1
-2
/
+0
2015-10-05
more work towards RVC 1.8
Andrew Waterman
1
-9
/
+2
2015-10-02
work towards rvc 1.8
Andrew Waterman
1
-3
/
+17
2015-09-04
Move towards RVC v1.8
Andrew Waterman
1
-10
/
+4
2015-05-31
New RV64C proposal
Andrew Waterman
1
-19
/
+63
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