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2020-05-19fdt: add pmp parsing helperChih-Min Chao2-1/+17
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-19fdt: restructure dtb create and config flowChih-Min Chao2-17/+50
1. pass dtb option from constructor 2. separate dtb generation from rom initialization 3. setup clint base from dtb Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-19fdt: option: add --dtb option to specify dtb binary fileChih-Min Chao2-2/+22
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-19fdt: add clint base address parsing helperChih-Min Chao2-0/+65
borrow from OpenSBI Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-19fdt: import fdt library from OpenSBIChih-Min Chao1-0/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-19Add missing stdexcept importsSchuyler Eldridge1-0/+1
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-05-19rvv: fix widen checkingChih-Min Chao2-4/+11
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-19rvv: store eew and emul to P.VU for unit/stride load/storeChih-Min Chao2-23/+22
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-18rvv: fix unit/stride emul calculationChih-Min Chao1-3/+3
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-18rvv: fix compiler warningChih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-18rvv: fix unit/strided load/store checking ruleChih-Min Chao1-29/+18
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-18rvv: vid's mlen overlap checkingDave.Wen1-1/+1
2020-05-18rvv: MLEN=1 overlappingDave.Wen1-4/+4
2020-05-17rvv: mlen=1 WIPDave.Wen2-4/+5
2020-05-14rvv: amo: only allow 32/64 bit elementChih-Min Chao2-16/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-14rvv: add vzext/vsextChih-Min Chao8-0/+44
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-14rvv: op: reorder vextChih-Min Chao1-18/+18
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-14rvv: dont't explicit throw exceptionChih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-14rvv: fix the fractional lmulDave.Wen2-8/+19
2020-05-13rvv: wrong operation to the fractional LMUL bitDave.Wen1-1/+1
2020-05-13rvv: amo: fix wrong index eewChih-Min Chao27-27/+27
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-13rvv: change to 0.9amoChih-Min Chao48-83/+218
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-13rvv: amo pre-0.9Chih-Min Chao13-0/+89
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-13rvv: fractional_lmul when lmul < 1Dave.Wen4-10/+20
2020-05-13vtype: fix the vta and vma functions and debugging displayDave.Wen3-3/+6
2020-05-13eew: add eewDave.Wen1-8/+17
2020-05-13eew: fix the eew=0 caseDave.Wen2-13/+18
2020-05-12rvv: add ext opcodeChih-Min Chao1-0/+18
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-12rvv: op: change vfunary0 and funary1 func6 fieldChih-Min Chao1-47/+47
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-12rvv: ldst: add missng check for VI_LDChih-Min Chao1-2/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-11rvv: change to 0.9 ldstChih-Min Chao78-451/+638
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-07rvv: add eew and lmul for vle/vse/vleffDave.Wen4-7/+39
2020-05-06fractional_lmul: update the vtype register and alos remove the useless reg_maskDave.Wen1-1/+3
2020-05-04zfh: implementation all instructionsChih-Min Chao37-0/+206
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-04zfh: op: add scalar opcodeChih-Min Chao1-0/+108
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-29zfh: zfh require F extension supportChih-Min Chao1-0/+3
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-27rvv: align VCSR with upstreamChih-Min Chao2-15/+13
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-27parse: refine error format reportingChih-Min Chao1-10/+24
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-27rvv: commitlog: fix comparision dst informationChih-Min Chao3-6/+9
Comparison only writes one vector register Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-24rvv: commitlog: fix missing informaiton for slide1Chih-Min Chao4-12/+12
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-24rvv: commitlog: fix dst information for int comparisonChih-Min Chao1-20/+40
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-23build: quota string with [] to avoid part of string missingChih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-23rvv: fix vfncvt.xu.f.w for fp16Chih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-23rvv: aad fp16 support for vfwxxx.[wv]vChih-Min Chao10-8/+47
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-22rvv: fix segment load/store nf checkingChih-Min Chao2-9/+11
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-21rvv: fix vfmv for fp16Chih-Min Chao3-13/+36
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-21rvv: fix vfmerge.vfm for fp16Chih-Min Chao1-2/+15
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-21rvv: fix vfslide for fp16Chih-Min Chao2-0/+16
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-21rvv: fix floating comparison for fp16Chih-Min Chao10-11/+49
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-21rvv: allow fp16Chih-Min Chao1-1/+2
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
generated by cgit v1.1 at 2024-08-07 04:28:55 +0000