| Age | Commit message (Collapse) | Author | Files | Lines |
|---|
|
|
|
This will also make it easier to support discontiguous hart IDs.
|
|
|
|
This commit started as an attempt to make the PLIC tolerant of
discontiguous hart IDs, but it turns out it was already most of
the way there: PLIC contexts can still be dense even if the hart
IDs are not.
Nevertheless, I wanted to avoid passing the procs vector directly to
the plic_t constructor. In removing it, I realized I could also get
rid of the smode parameter by querying whether each hart has S-mode.
This is also more correct; previously, we were instantiating the PLIC
as though all harts had S-mode, regardless of whether they actually did.
|
|
|
|
|
|
|
|
The general strategy is to avoid iterating over the ID space.
|
|
|
|
This implements the Zicond (conditional integer operations) extension,
as of version 1.0-draft-20230120.
The Zicond extension acts as a building block for branchless sequences
including conditional-arithmetic, conditional-logic and
conditional-select/move.
The following instructions constitute Zicond:
- czero.eqz rd, rs1, rs2 => rd = (rs2 == 0) ? 0 : rs1
- czero.nez rd, rs1, rs2 => rd = (rs2 != 0) ? 0 : rs1
See
https://github.com/riscv/riscv-zicond/releases/download/v1.0-draft-20230120/riscv-zicond_1.0-draft-20230120.pdf
for the proposed specification and usage details.
|
|
Note this encoding.h's history is unusual because riscv-opcodes master
is currently incompatible with Spike. See the PR that contains its
commit hash (https://github.com/riscv/riscv-opcodes/pull/157) and
discussion at https://github.com/riscv-software-src/riscv-isa-sim/pull/1234#discussion_r1092243338
|
|
|
|
|
|
|
|
|
|
D-mode, then enter D-mode and ignore breakpoint exception
|
|
|
|
The addition of Svadu support and removal of --mmu-dirty
command line flag results in the dirty_enabled configuration state
no longer being used. Remove the remnants of this state.
|
|
The Svadu (https://github.com/riscv/riscv-svadu) extension updates
the A/D bits of PTEs:
1. In S/HS mode when menvcfg.hade=1
2. In G-stage page tables when menvcfg.hade=1
3. In VS mode when henvcfg.hade=1
To enable this behavior the 'svadu' ISA string is needed.
This newly added behavior supplants the --mmu-dirty flag. However,
that flag is not yet removed.
|
|
Add in the support for the HADE fields in menvcfg and henvcfg
based off of the svadu ISA string. This only allows for the writable
HADE bits being exposed when the svadu ISA string is employed. No
other behavior is implemented.
|
|
The Svadu extension adds a HADE field (bit 61) to both
menvcfg and henvcfg. Add the definitions so they can be utilized.
|
|
Make the ISA parser understand the Svadu extension.
|
|
|
|
No reason to check it both in sim_t::sim_t and in processor_t::set_pmp_num.
|
|
|
|
|
|
|
|
Now that we guarantee that max_isa and extension_table are synchronized,
we only need to check the latter.
|
|
This fixes a bug where --isa=rv64imafdc would fail to set
extension_table['F'] because of the ad hoc manner in which we were
synchronizing max_isa and extension_table.
|
|
We know its size at compile time.
|
|
Add new accessors that accept the isa_extension_t enum.
Retain the original ones that accept unsigned char to avoid churn.
|
|
Add legalize_timing() for tdata1.timing
|
|
Since this method does not use 'this', we turn this method into static.
|
|
Since this method no longer use 'this', we turn this method into static.
|
|
avoid breaking functionality by reordering statements in tdata1.write()
|
|
As recommended in the debug spec table "Suggested Trigger Timings", to
avoid the footgun of replaying a load (which may have side effects) when
the breakpoint trap handler returns.
reference: https://github.com/riscv-software-src/riscv-isa-sim/pull/1208#issuecomment-1373035906
-----------------------------------------------------------------------
The legalize_timing() depends on select, execution, load, and store,
which are updated in the same function tdata1_write(). As a result,
reordering statements in the tdata1_write() may break the functionality.
Passing those variables as parameters to legalize_timing() does not
solve the problem. Thus, we give the original write value and the masks
of the variables to the legalize_timing(). This makes the legalization
function independent of the updating variables and resolves the issue.
reference: https://github.com/riscv-software-src/riscv-isa-sim/pull/1214
|
|
Run Spike and HTIF in a single thread, rather than two
|
|
|
|
|
|
The two-thread approach was originally motivated by making Spike look
as similar as possible to other HTIF targets. But we can get the same
semantics without threading by running the simulator inside of the HTIF
host's idle loop instead of performing a context switch.
This was motivated by speeding up the simulator on Mac OS (it's worth
around 20% because using pthread condition variables to force strict
alternation is very slow). But I think it also simplifies the control
flow enough to justify it on that basis, too.
|
|
On my Mac Mini, calling `poll()` on stdin takes around 10 us, and we
are invoking it every 20 us or so. Reduce the frequency of polling
by 16x when not actively receiving data, thereby reducing the fraction
of time spent in `poll()` to a trivial amount.
|
|
space border
|
|
The method can simplify proper processing of sitiations when
(base + size) overflows 64-bit interger.
|
|
NFT. We also mark `base` and `size` fields as private.
|
|
NFC. The intention is for `base` and `size` fields of mem_cfg_t
to be private members. This is the fist part of this commit.
|
|
It dates back to when this code was ifdef'd.
|
|
This is worth a 1.4x speedup on the slow path (when not histogramming).
|
|
|
|
|
|
|
