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rocket-tools/riscv-gnu-toolchain/spike.git
confprec
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dts_parsing
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Author
Files
Lines
2022-12-21
triggers: refactor: update trigger_t::mode_match()
YenHaoChen
1
-5
/
+5
2022-12-21
triggers: refactor: add trigger_t::mode_match() function
YenHaoChen
2
-14
/
+14
2022-12-20
Support more than 65 Z* extensions
Andrew Waterman
1
-1
/
+1
2022-12-21
triggers: refactor: move m/s/u/vs/vu to trigger_t
YenHaoChen
1
-15
/
+6
2022-12-21
triggers: refactor: add mcontrol.vs and mcontrol.vu
YenHaoChen
2
-3
/
+4
2022-12-21
triggers: refactor: cleaner vs and vu checking
YenHaoChen
1
-8
/
+4
2022-12-20
Always build with commit logging support
Jerry Zhao
4
-18
/
+3
2022-12-20
Add logged instruction variants to insn_desc_t
Jerry Zhao
3
-17
/
+46
2022-12-20
Add logged variants of insn templates
Jerry Zhao
6
-18
/
+36
2022-12-20
Replace compile-time commitlog check with runtime check for vector writes
Jerry Zhao
1
-3
/
+1
2022-12-20
Replace compile-time conditional with run-time conditional for load/store log...
Jerry Zhao
1
-19
/
+4
2022-12-20
Split execute_insn into fast and logged variants
Jerry Zhao
1
-14
/
+9
2022-12-20
Force slow-path when commit-logging is enabled
Jerry Zhao
1
-1
/
+1
2022-12-20
Always compile commit-log utility functions
Jerry Zhao
1
-2
/
+0
2022-12-20
Check commitlog-enable dynamicallly for csr_t::log_special_write
Jerry Zhao
1
-4
/
+2
2022-12-20
Always reset commit logging variables
Jerry Zhao
1
-2
/
+0
2022-12-20
Always perform symbol lookup in debug
Jerry Zhao
2
-7
/
+5
2022-12-20
Fix compile error in commit-logging code
Jerry Zhao
1
-3
/
+3
2022-12-20
Allow reads/writes to reserved CLINT regions
Jerry Zhao
1
-0
/
+4
2022-12-17
arith.h: remove redundant y1 = t; in mulhu(uint64_t, uint64_t)
Serdar Sayın
1
-1
/
+0
2022-12-16
Remove processor.h/sim.h -> config.h dependencies
Jerry Zhao
2
-2
/
+0
2022-12-16
Add missing vector_unit.h to install headers list
Jerry Zhao
1
-1
/
+2
2022-12-16
Remove entropy_source.h -> internals.h dependency
Jerry Zhao
1
-1
/
+0
2022-12-16
Add missing abstract_interrupt_controller.h to header lists
Jerry Zhao
1
-0
/
+2
2022-12-16
Remove debug_module.h -> mmu.h dependency
Jerry Zhao
1
-1
/
+2
2022-12-15
Use relative include paths to support public usage of these headers
Jerry Zhao
2
-2
/
+2
2022-12-15
Don't install instruction decode macros
Jerry Zhao
1
-3
/
+1
2022-12-15
Add config.h includes directly to source files instead of relying on header c...
Jerry Zhao
4
-0
/
+4
2022-12-15
Merge pull request #1182 from riscv-software-src/fix-1180
Andrew Waterman
1
-0
/
+1
2022-12-15
Merge pull request #1181 from riscv-software-src/better-error-message
Andrew Waterman
1
-1
/
+6
2022-12-15
Fix build broken by #1170 and #1180
Andrew Waterman
1
-0
/
+1
2022-12-15
Merge pull request #1180 from ucb-bar/cleancfg
Andrew Waterman
9
-30
/
+45
2022-12-15
Print better error message when requesting >1024 harts
Andrew Waterman
1
-1
/
+6
2022-12-15
Rename memif_endianness_t to endianness_t
Jerry Zhao
7
-16
/
+16
2022-12-15
Pull memif_endianness_t into cfg.h
Jerry Zhao
2
-1
/
+6
2022-12-15
Add cfg.cc to hold internal implementation of mem_cfg_t
Jerry Zhao
3
-16
/
+26
2022-12-15
Split decode.h into public decode.h and private decode_macros.h
Jerry Zhao
9
-312
/
+328
2022-12-14
Merge pull request #1175 from riscv-software-src/fix-mac-build
Andrew Waterman
1
-0
/
+1
2022-12-14
Fix build on M1
Andrew Waterman
1
-0
/
+1
2022-12-13
Move boost asio socket interface to socketif_t
Jerry Zhao
6
-86
/
+143
2022-12-13
Merge pull request #1173 from ucb-bar/splitvu
Andrew Waterman
9
-207
/
+245
2022-12-12
Make the processor_t interface independent of configure'd variables (#1174)
Jerry Zhao
3
-14
/
+8
2022-12-12
Pull vector unit into separate source/header
Jerry Zhao
7
-205
/
+243
2022-12-12
Pull p/v_ext_macros.h out of decode.h
Jerry Zhao
2
-2
/
+2
2022-12-10
Move mhselect_compare into mhselect_interpretation
Scott Johnson
2
-5
/
+5
2022-12-10
Use interpret_mhselect() to decide textra compare mode
Scott Johnson
2
-17
/
+2
2022-12-10
Interpret mhselect in centralized place
Scott Johnson
2
-12
/
+28
2022-12-10
triggers: add mcontext and hcontext CSRs
YenHaoChen
3
-7
/
+15
2022-12-10
triggers: add scontext CSR
YenHaoChen
3
-2
/
+13
2022-12-10
triggers: checking textra (tdata3); checking ASID and VMID
YenHaoChen
2
-2
/
+57
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