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2019-04-02Implement debug hasel support (#287)Tim Newsome6-72/+138
2019-03-31Add fesvr; only globally install fesvr headers/libsstatic-linkAndrew Waterman1-11/+0
2019-03-30RV32Q is not invalidAndrew Waterman1-3/+0
2019-03-27Respect interrupt priorities even when not delegatedAndrew Waterman1-9/+13
2019-03-12include sys/types.h for suseconds_t (#285)nmeum1-0/+1
2019-03-04Implement halt groups (#280)Tim Newsome3-176/+649
2019-02-28Further fix PMP checks for partially-matching accesses (#270)Andrew Waterman1-3/+4
2019-02-04Fix use of old name `riscv-isa-run` (#269)Luís Marques1-1/+1
2019-02-04fixing compilation errors on openbsdDinesh Thirumurthy1-0/+7
2019-01-28Fix PMP checks for partially-matching accesses (#270)Andrew Waterman2-8/+21
2019-01-09Merge pull request #265 from riscv/debug_testTim Newsome6-36/+84
2018-12-21Reserve the PMP R=0 W=1 combinationAndrew Waterman1-2/+5
2018-12-19Flush I/O buffers before forkingAndrew Waterman1-0/+1
2018-12-13Add --dmi-rti and --abstract-rti to test OpenOCD.Tim Newsome6-36/+84
2018-12-03Correct address autoincrement calls. (#263)Tim Newsome1-2/+5
2018-11-06Report misaligned-address exception on failed store-conditionalsAndrew Waterman2-14/+8
2018-10-18Provide a noisy until interactive commandHesham Almatary2-6/+20
2018-10-04Set marchid to assigned value 5Andrew Waterman1-1/+1
2018-09-27Add comment about CSR read side effectsAndrew Waterman1-0/+3
2018-09-25For backwards compatibility, reset PMP to permit all accessesAndrew Waterman1-0/+3
2018-09-25Add PMP supportAndrew Waterman4-24/+147
2018-09-24Add "--log-cache-miss" option to generate a log of cache miss. (#241)takeoverjp2-2/+14
2018-09-05Fix cut-and-paste bug in 64-bit SBA loads.Tim Newsome1-1/+1
2018-08-23Add dummy custom debug registers, to test OpenOCD. (#233)Tim Newsome2-0/+18
2018-08-23Fix several disassembler bugsAndrew Waterman1-0/+1
2018-08-23Add --disable-dtb option to suppress writing the DTB to memoryAndrew Waterman2-2/+7
2018-08-22Make IRQ_COP read-only/undelegable unless coprocessor is presentAndrew Waterman1-1/+2
2018-08-21Instantiate disassembler after max_xlen is knownAndrew Waterman1-1/+5
2018-08-17Don't increment instret immediately after it is written (#231)Andrew Waterman1-0/+6
2018-08-10Fix 2 trigger corner cases. (#229)Tim Newsome2-6/+14
2018-07-31Make sstatus.MXR readableAndrew Waterman1-1/+1
2018-07-23Fix using the uninitialized disassemble object. (#220)SeungRyeol Lee1-1/+1
2018-07-10Refactor and fix LR/SC implementation (#217)Andrew Waterman9-11/+34
2018-06-11Update debug_defines.hTim Newsome3-285/+303
2018-05-31Put simif_t declaration in its own file. (#209)Andy Wright7-16/+27
2018-05-18Fix install of missed header. (#207)Prashanth Mundkur1-0/+1
2018-05-18Extract out device-tree generation and compilation into an exported api. (#197)Prashanth Mundkur4-142/+175
2018-05-04Revert "C.LWSP and C.LDSP with rd=0 are legal instructions"Andrew Waterman2-0/+2
2018-05-03C.LWSP and C.LDSP with rd=0 are legal instructionsAndrew Waterman2-2/+0
2018-04-30Fix commit log for serializing instructionsAndrew Waterman1-1/+1
2018-04-30Only break out of the simulator loop on WFI, not on CSR writesAndrew Waterman3-2/+9
2018-04-04Allow querying the mmu configuration chosen during the build. (#191)Prashanth Mundkur1-0/+18
2018-04-04Revert "Fix for issue #183: No illegal instruction exception for c.sxxi instr...Andrew Waterman3-3/+3
2018-03-26Add an api to get the name for a CSR.Prashanth Mundkur2-0/+10
2018-03-21Implement Hauser misa.C misalignment proposal (#187)Andrew Waterman4-6/+12
2018-03-21Fix the access exception during page-table walks to match the original access...Prashanth Mundkur1-1/+9
2018-03-19Fix spike-dasm. (#184)Tim Newsome1-1/+2
2018-03-16Implement debug havereset bitsTim Newsome5-1/+33
2018-03-16Fix for issue #183: No illegal instruction exception for c.sxxi instructions ...Shubhodeep Roy Choudhury3-3/+3
2018-03-14Fix a bug caused by moving misa into state_t. (#180)Prashanth Mundkur2-3/+4
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