index
:
rocket-tools/riscv-gnu-toolchain/spike.git
confprec
cs250
cycleh
debug_rom
debug_rom_fence
device_flags
dtm_reset_error
dts_parsing
dynamic
eos18-bringup
factor-out-macros
fix-bf16
force-rtti
fp-encoding
heterogeneous_mc
hwachav4
increase-stack-size
itrigger-etrigger-cleanup
load_reservation_set_size
log-commits-faster
master
mmio-hack
mvp
no_progbuf
no_progbuf2
nolibfdt
p-ext-0.5.2
plctlab-plct-zce-fix2
plic-clint-endian
plic_uart_v1
priv-1.10
private-l1-caches
pte-info-and-delegation
remove-tests
rivosinc-etrigger_fix_exception_match
rva-profile-support
simplify-misaligned
sodor
sparse-mem
speedup-hacks
static-link
test
tmp
trigger_priority
tweak_debug_rom
whole-archive
sifive/rvv0.9-phase2
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
riscv
/
sim.cc
Age
Commit message (
Expand
)
Author
Files
Lines
2020-05-20
add configurable LR/SC reservation set
Dave.Wen
1
-0
/
+5
2020-05-19
Support consuming PMP number and granularity from DTB
Andrew Waterman
1
-0
/
+9
2020-05-19
fdt: restructure dtb create and config flow
Chih-Min Chao
1
-8
/
+45
2020-05-19
fdt: option: add --dtb option to specify dtb binary file
Chih-Min Chao
1
-2
/
+17
2020-04-05
Fix debug segfault by partially reverting #409
Andrew Waterman
1
-2
/
+3
2020-04-05
Write execution logs to a named log file (#409)
Rupert Swarbrick
1
-25
/
+33
2020-03-04
rvv: remove the option of vector misaligned access
Zhen Wei
1
-2
/
+0
2020-03-04
rvv: remove the option of vector impl. check
Zhen Wei
1
-4
/
+0
2020-02-19
Make CLINT API use Hz instead of MHz
Andrew Waterman
1
-1
/
+1
2020-02-19
Add optional support for real-time clint
Anup Patel
1
-2
/
+3
2020-02-19
Make spike capable of booting Linux
Anup Patel
1
-3
/
+3
2019-11-17
Add --priv option to control which privilege modes are available
Andrew Waterman
1
-3
/
+4
2019-10-29
Implement support for big-endian hosts
Marcus Comstedt
1
-2
/
+5
2019-10-22
Enforce 2^56-bit physical address limit
Andrew Waterman
1
-2
/
+9
2019-09-29
Adds --log-commits commandline option. (#323)
dave-estes-syzexion
1
-1
/
+10
2019-09-04
rvv: exit when there is unsupported instructions
Chih-Min Chao
1
-0
/
+1
2019-09-04
rvv: reimplement check-1905 as check-impl
Chih-Min Chao
1
-1
/
+3
2019-09-04
Implement MMIO device plugins.
Aaron Jones
1
-4
/
+8
2019-08-02
rvv: add vector-mistrp option
Chih-Min Chao
1
-2
/
+1
2019-06-06
rvv: refine trailing space
Chih-Min Chao
1
-1
/
+1
2019-05-29
Clean up debug module options. (#299)
Tim Newsome
1
-7
/
+3
2019-05-20
rvv: add --check-1905 option to turn on 1905 release check
Chih-Min Chao
1
-0
/
+4
2019-05-14
Add --debug-no-abstract-csr (#267)
Tim Newsome
1
-2
/
+4
2019-05-14
Implement debug hasel support (#287)
Tim Newsome
1
-2
/
+2
2019-04-30
rvv: configurable vector architecture during configuration and
Dave.Wen
1
-4
/
+4
2019-04-06
Add --dmi-rti and --abstract-rti to test OpenOCD.
Tim Newsome
1
-2
/
+4
2018-08-23
Add --disable-dtb option to suppress writing the DTB to memory
Andrew Waterman
1
-2
/
+3
2018-07-10
Refactor and fix LR/SC implementation (#217)
Andrew Waterman
1
-1
/
+1
2018-05-18
Extract out device-tree generation and compilation into an exported api. (#197)
Prashanth Mundkur
1
-142
/
+2
2018-03-16
Implement debug havereset bits
Tim Newsome
1
-0
/
+5
2018-03-07
Merge pull request #177 from riscv/debug_auth
Tim Newsome
1
-2
/
+3
2018-03-06
Narrow the interface used by the processors and memory to the top-level simul...
Prashanth Mundkur
1
-3
/
+3
2018-02-27
Add debug module authentication.
Tim Newsome
1
-2
/
+3
2018-02-01
Add --debug-sba option
Tim Newsome
1
-2
/
+3
2018-01-18
Support debug system bus access.
Tim Newsome
1
-4
/
+3
2017-12-11
Make progbuf a run-time option.
Tim Newsome
1
-2
/
+4
2017-11-15
Merge pull request #156 from p12nGH/noncontiguous_harts
Andrew Waterman
1
-3
/
+14
2017-11-15
Support for non-contiguous hartids
Gleb Gagarin
1
-3
/
+14
2017-11-03
Put HTIF in the device tree
Palmer Dabbelt
1
-0
/
+3
2017-06-14
Support 64-bit start PCs in reset vector.
Tim Newsome
1
-12
/
+10
2017-05-16
Merge remote-tracking branch 'origin/debug-0.13' into priv-1.10
Palmer Dabbelt
1
-6
/
+6
2017-05-01
Fix segfault when accessing bad memory addresses
Andrew Waterman
1
-2
/
+3
2017-05-01
Set default entry point from ELF
Andrew Waterman
1
-2
/
+6
2017-04-30
Add option to set start pc
Andrew Waterman
1
-8
/
+18
2017-04-30
Support more flexible main memory allocation
Andrew Waterman
1
-24
/
+21
2017-04-17
Merge remote-tracking branch 'origin/priv-1.10' into HEAD
Megan Wachs
1
-48
/
+156
2017-03-30
fdt: move interrupt controller into its own node
Wesley W. Terpstra
1
-4
/
+7
2017-03-24
Default to 2 GiB of memory
Andrew Waterman
1
-1
/
+1
2017-03-22
riscv: replace rtc device with a real clint implementation
Wesley W. Terpstra
1
-13
/
+11
2017-03-21
sim: declare cores as interrupt-controllers for clint
Wesley W. Terpstra
1
-0
/
+2
[next]