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AgeCommit message (Expand)AuthorFilesLines
2019-04-24rvv: fix sign-injection namingChih-Min Chao1-4/+4
2019-04-24fixed the vfunary*_vv decodingDave.Wen1-0/+2
2019-04-18rvv: add vsetvlDave1-0/+1
2019-04-03rvv: remove the redundant targetDave.Wen1-1/+0
2019-04-03rvv: add missing instruction to makefileChih-Min Chao1-0/+108
2019-04-02rvv: add missing file to makefileChih-Min Chao1-0/+10
2019-04-01rvv: add missing target in the riscv.mk.inDave.Wen1-7/+8
2019-03-28rvv: add missing vfsgn?_vf makefile entriesChih-Min Chao1-0/+3
2019-03-28rvv: add vlx[whb][u].v and vsx[whb].vChih-Min Chao1-0/+9
2019-03-28rvv: add vls[whb][u].v and vss[whb].vChih-Min Chao1-0/+7
2019-03-27rvv: add vl[whb][u].v and vs[hb].vChih-Min Chao1-0/+7
2019-03-26rvv: remove duplicated instruction item in makefileChih-Min Chao1-5/+0
2019-03-26declare vector instructions without VFUNARY0/1 and VMUNARY0Dave.Wen1-0/+139
2019-03-26rvv: merge vssseg[3-6]w.v into vssw.vChih-Min Chao1-4/+1
2019-03-26rvv: merge vlsseg[3-6]w.v into vlsw.vChih-Min Chao1-4/+1
2019-03-25rvv: merge vsseg[3-6]w.v into vsw.vChih-Min Chao1-1/+0
2019-03-25rvv: merge vlseg[3-6]w.v into vlw.vChih-Min Chao1-1/+0
2019-02-22implement some float opertions and vmv, no-op implementations for segmented l...Bruce Hoult1-0/+15
2019-02-13Update to 20190131 specBruce Hoult1-1/+1
2019-02-04Add enough instructions for saxpy and sgemmBruce Hoult1-0/+4
2019-01-21Add FLH and FSH instructions expanding IEEE fp16 in memory to fp32 in registersBruce Hoult1-0/+2
2018-05-31Put simif_t declaration in its own file. (#209)Andy Wright1-0/+1
2018-05-18Fix install of missed header. (#207)Prashanth Mundkur1-0/+1
2018-05-18Extract out device-tree generation and compilation into an exported api. (#197)Prashanth Mundkur1-0/+2
2017-09-28Implement Q extensionAndrew Waterman1-0/+32
2017-05-16Merge remote-tracking branch 'origin/debug-0.13' into priv-1.10Palmer Dabbelt1-2/+4
2017-04-25FMV.X.S/FMV.S.X -> FMV.X.W/FMV.W.XAndrew Waterman1-2/+2
2017-04-17debug: Compiles again with new debug_defines.h file, but not tested.Megan Wachs1-2/+0
2017-04-17Merge remote-tracking branch 'origin/priv-1.10' into HEADMegan Wachs1-1/+3
2017-03-22riscv: replace rtc device with a real clint implementationWesley W. Terpstra1-1/+1
2017-02-15sfence.vm -> sfence.vmaAndrew Waterman1-1/+1
2017-02-06Refactor remote bitbang code.Tim Newsome1-0/+2
2017-02-03OpenOCD connects, and sends some data that we receive.Tim Newsome1-2/+2
2016-06-22Remove legacy HTIF; implement HTIF directlyAndrew Waterman1-2/+0
2016-05-23Add dret.Tim Newsome1-0/+1
2016-05-23Add debug_module bus device.Tim Newsome1-0/+2
2016-05-23Listen on a socket for gdb to connect to.Tim Newsome1-0/+2
2016-05-19Removed devicetree.h from riscv.mk.in since it no longer existsacw12511-1/+0
2016-05-18Added missing header files to riscv.mk.inacw12511-0/+3
2016-04-28Remove MTIME[CMP]; add RTC deviceAndrew Waterman1-0/+2
2016-04-19Split ERET into URET, SRET, HRET, MRETAndrew Waterman1-2/+3
2016-03-02WIP on priv spec v1.9Andrew Waterman1-3/+0
2015-11-12Generate device tree for target machineAndrew Waterman1-0/+1
2015-10-20Update to hopefully final RVC 1.9 encodingAndrew Waterman1-2/+0
2015-10-05more work towards RVC 1.8Andrew Waterman1-2/+0
2015-10-02work towards rvc 1.8Andrew Waterman1-1/+11
2015-09-10Fix non-portable sed commands generating insn_list.hAlbert Ou1-1/+3
2015-09-08Improve instruction fetchAndrew Waterman1-1/+200
2015-05-13Install "disasm.h"Palmer Dabbelt1-0/+1
2015-04-03Support setting ISA/subsets with --isa flagAndrew Waterman1-1/+2
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