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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2018-05-18 13:38:57 -0700 |
|---|---|---|
| committer | Andrew Waterman <aswaterman@gmail.com> | 2018-05-18 13:38:57 -0700 |
| commit | 08cc9e2da68800c96bc6966c2501554e0a56d0c5 (patch) | |
| tree | 1662c0bf0da9631f4852317c3c94d710f87218a9 /riscv/riscv.mk.in | |
| parent | 2b4106fc006418b0446166b01848089594a5c771 (diff) | |
| download | spike-08cc9e2da68800c96bc6966c2501554e0a56d0c5.zip spike-08cc9e2da68800c96bc6966c2501554e0a56d0c5.tar.gz spike-08cc9e2da68800c96bc6966c2501554e0a56d0c5.tar.bz2 | |
Extract out device-tree generation and compilation into an exported api. (#197)
Diffstat (limited to 'riscv/riscv.mk.in')
| -rw-r--r-- | riscv/riscv.mk.in | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index f8abb1b..233953f 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -11,6 +11,7 @@ riscv_hdrs = \ decode.h \ devices.h \ disasm.h \ + dts.h \ mmu.h \ processor.h \ sim.h \ @@ -33,6 +34,7 @@ riscv_precompiled_hdrs = \ riscv_srcs = \ processor.cc \ execute.cc \ + dts.cc \ sim.cc \ interactive.cc \ trap.cc \ |