| Age | Commit message (Collapse) | Author | Files | Lines |
|---|
|
|
|
1. fix the ELAN check for vill
2. handle 'rs1 = x0'
3. make logic more readable
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
|
|
|
|
Mask calculation was not in consistency with debug spec.
Watch debug spec. 5.2.7 match field overview and
debug spec. B.9 fourth example.
Mask should not cover LSB zero bit.
Also there is a way to make it simplier:
reg_t mask = ~(((~state.tdata2[i]) - 1) ^ ~state.tdata2[i]);
|
|
* Extends the commit log feature with memory writes.
This provides a little more information for debugging instruction
traces, allowing you to maintain the state of memory as the trace
is processed.
The following sample trace output illustrates the formatting of
the new memory writes. The first line is an instruction at
location 0x80000094, containing the bytes (0x80830313) and
commiting the value 0x80000898 to the register x6. The second
line is an instruction which neither commits a register nor
writes memory. The third line writes the value 0x0 to
0x80000890.
3 0x80000094 (0x80830313) x 6 0x80000898
3 0x80000098 (0x0062d663)
3 0x8000009c (0x00028023) mem 0x80000890 0x0
* Changes addressing feedback from review.
|
|
* Adds --log-commits commandline option.
Similar to histogram support, the commit logging feature must be
enabled with a configure option: --enable-commitlog. However, unlike
that feature, there was no way to turn off the logging with a
commandline option once the functionality was built in. This (git)
commit provides that abilty.
* Changes addressing review feedback.
|
|
* Don't corrupt s0 when abstract CSR write fails.
* Support abstract FPR access then mstatus.FS=0
Discussion on the spec list leans towards this being a requirement.
Certainly users want their debugger to be able to access all registers
regardless of target state.
|
|
In the previous scheme, debug-mode software could exit debug mode by
zeroing the dcsr.cause field. While benign, that behavior is out of
spec.
|
|
the default vector parameters are defined in configuration time but can
be changed throught command-line option
Signed-off-by: Dave Wen <dave.wen@sifive.com>
|
|
Signed-off-by: Bruce Hoult <bruce@hoult.org>
Signed-off-by: Dave Wen <dave.wen@sifive.com>
|
|
|
|
- Use physical addresses to avoid homonym ambiguity (closes #215)
- Yield reservation on store-conditional (https://github.com/riscv/riscv-isa-manual/commit/03a5e722fc0fe7b94dd0a49f550ff7b41a63f612)
- Don't yield reservation on exceptions (it's no longer required).
|
|
See https://github.com/riscv/riscv-isa-manual/commit/0472bcdd166f45712492829a250e228bb45fa5e7
- Reads of xEPC[1] are masked when RVC is disabled
- Writes to MISA are suppressed if they would cause a misaligned fetch
- Misaligned PCs no longer need to be checked upon fetch
|
|
* Fix misa losing its value in processor constructor due to state:reset() following state.misa initialization.
Make state:reset() preserve misa.
* Set state.misa to max_isa on reset().
* Idiomatic fix for earlier commit.
|
|
|
|
simulator/htif.
This allows the implementation of an alternative top-level simulator class.
|
|
The installed header files from the riscv subproject were incomplete, since
processor.h includes debug_rom_defines.h, and the latter was not installed.
Fix by moving it into riscv/, add it to the riscv subproject header list, which
ensures it will get installed. While here, also add a missed dependency of debug_rom
on riscv/encoding.h to debug_rom/Makefile.
|
|
See https://github.com/riscv/riscv-isa-manual/pull/139
Not adopted yet, but I'm putting the implementation here for reference.
|
|
|
|
|
|
It's supplanted by the hypervisor extension, which doesn't use the privilege
encoding of 2; it still looks like supervisor (i.e. 1).
|
|
|
|
* Fix commit-log for Q extension, and for RV32
The number of nibbles printed out now depends upon XLEN or FLEN,
as appropriate.
* Factor out FLEN calculation
|
|
Specifically, don't print out the execution count if the same
instruction is executed by different harts.
|
|
In an older implementation I was thinking of having different entry
points for different harts, but that's no longer true.
Also get rid of a bunch of trailing whitespace.
|
|
bugs.
|
|
|
|
|
|
|
|
https://github.com/riscv/riscv-isa-manual/issues/10
|
|
|
|
|
|
|
|
|
|
Conflicts:
riscv/encoding.h
riscv/processor.cc
|
|
Add timing bit (but it doesn't do anything).
Implement dmode bit.
|
|
|
|
|
|
|
|
|
|
So far I only have testcases for instruction and data address.
Not implemented is the mechanism that lets the debugger prevent a user
program from using triggers at all. I'll be adding that soonish.
The critical path is unchanged, but my experimenting shows the
simulation is slowed down about 8% by this code. Reducing the size of
trigger_match() (which is never called during my benchmark) fixes that,
but making it not be inlined has no effect. I suspect the slowdown comes
from cache alignment or something similar, and on a different CPU or
after more code changes the speed will come back.
|
|
Either approach is legal, but this more closely matches Rocket.
|
|
Users can use this register to inspect and change the privilege level of
the core. It doesn't make any assumptions about the actual underlying
debug mechanism (as opposed to having the user change DCSR directly,
which may not exist in all debug implementations).
|
|
The interpretation of RVC opcodes depends on XLEN, and the disassembler
always assumed RV32.
h/t Michael Clark
|
|
|
|
|
|
Added a test, too.
|
|
|
|
|
|
This should replace the ROM hack I implemented earlier, but for now both
exist together.
Back to the point where gdb connects, core jumps to ROM->RAM->ROM.
|
