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AgeCommit message (Expand)AuthorFilesLines
2019-11-17mstatus.FS only exists if (S || V || F)Andrew Waterman1-1/+5
2019-11-17Remove S-mode interrupts when S-mode not presentAndrew Waterman1-5/+12
2019-11-17Fix mode-transition logic when S-mode not presentAndrew Waterman1-1/+1
2019-11-17Add --priv option to control which privilege modes are availableAndrew Waterman1-2/+27
2019-11-17Factor out boilerplate strtolower functionAndrew Waterman1-3/+9
2019-11-17In parse_isa_string, populate max_isa rather than state.misaAndrew Waterman1-7/+3
2019-11-11Revert "rvv: make vxrm/vxsat readable from FCSR"Chih-Min Chao1-22/+5
2019-11-11rvv: remove tail-zeroChih-Min Chao1-4/+0
2019-10-30rvv: remove dead codeChih-Min Chao1-2/+0
2019-10-29rvv: make vxrm/vxsat readable from FCSRChih-Min Chao1-5/+22
2019-10-29rvv: fix marvelous vsetvlo againChih-Min Chao1-1/+1
2019-10-28Initialize histogram_enabled and log_commits_enabled in constructor (#354)Scott Johnson1-0/+1
2019-10-28rvv: fix rs1 == 0 when vlmax is not reducedChih-Min Chao1-1/+3
2019-10-22rvv: remove vmfordChih-Min Chao1-6/+0
2019-10-15rvv: add new rs1 = zero feature to vsetvlChih-Min Chao1-2/+13
2019-10-07rvv: refine vill/vl handling for invalid caseChih-Min Chao1-3/+5
2019-09-29Adds --log-commits commandline option. (#323)dave-estes-syzexion1-0/+13
2019-09-25rvv:add t0/t1 to configure to setup default tailzero modeChih-Min Chao1-0/+4
2019-09-09rvv: update missing inst in 1905 checkChih-Min Chao1-0/+3
2019-09-04rvv: add impl_table for instruction release checkChih-Min Chao1-0/+769
2019-09-04Remove statement with no effectAndrew Waterman1-1/+0
2019-07-22Set vtype.vill correctly; also reset it to trueAndrew Waterman1-3/+8
2019-07-22Check presence of V extension when accessing vector CSRsAndrew Waterman1-0/+15
2019-07-22VL and VTYPE aren't writable CSRsAndrew Waterman1-12/+0
2019-07-22Writing non-existent CSRs, access FPRs with mstatus.FS=0 (#311)Tim Newsome1-2/+7
2019-07-22Add debug_mode state bit, rather than overloading dcsr.causeAndrew Waterman1-4/+5
2019-07-22Fix support for 32-bit hosts (but no V extension in that case!)Andrew Waterman1-1/+5
2019-07-22Support S-mode vectored interruptsAndrew Waterman1-2/+3
2019-07-22Fix clang uninitialized variable warningAndrew Waterman1-1/+1
2019-06-12rvv: merge the vcsr to ordinary csr and remove the redundant functionsDave.Wen1-46/+31
2019-06-06rvv: remove trailing spaceChih-Min Chao1-2/+2
2019-06-04rvv: refine the code for checking the varch option setDave.Wen1-17/+13
2019-05-14RV32Q is not invalidAndrew Waterman1-6/+0
2019-05-14Respect interrupt priorities even when not delegatedAndrew Waterman1-9/+13
2019-05-02rvv: fix the spike isa optionDave.Wen1-6/+0
2019-04-30rvv: fixed type and removed redundant variableDave.Wen1-5/+3
2019-04-30rvv: decouple the vectorUnit to the processor's state.Dave.Wen1-8/+79
2019-04-30rvv: add isa extension VDave1-1/+7
2019-04-22fixed the wrong switch statement of set_vcsrDave.Wen1-33/+39
2019-04-20improve the vectorUint_tDave1-4/+11
2019-04-18fix the vsew decoding positionDave.Wen1-1/+1
2019-04-18rvv: support programming vcsrDave.Wen1-2/+27
2019-04-06Fix use of old name `riscv-isa-run` (#269)Luís Marques1-1/+1
2019-03-29processor: for rounding mode and config access functionsDave.Wen1-0/+8
2019-03-28vsetvli: if rs1 = x0, then use maximum vector lengthDave.Wen1-3/+3
2019-03-27rvv: add mlen for convenientChih-Min Chao1-0/+1
2019-03-27add vmul, sbc, and shift instructions.Dave.Wen1-0/+1
2019-03-04reduce VLEN to 128 so multiple iterations are needed on the test data used fo...Bruce Hoult1-1/+1
2019-02-24Add comparison of user state (XPR, FPR, VPR) after each instructionBruce Hoult1-4/+1
2019-02-08move vectorUnit_t::reset() and setVL() impl out of headerBruce Hoult1-0/+26
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