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riscv
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processor.cc
Age
Commit message (
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Author
Files
Lines
2019-11-17
mstatus.FS only exists if (S || V || F)
Andrew Waterman
1
-1
/
+5
2019-11-17
Remove S-mode interrupts when S-mode not present
Andrew Waterman
1
-5
/
+12
2019-11-17
Fix mode-transition logic when S-mode not present
Andrew Waterman
1
-1
/
+1
2019-11-17
Add --priv option to control which privilege modes are available
Andrew Waterman
1
-2
/
+27
2019-11-17
Factor out boilerplate strtolower function
Andrew Waterman
1
-3
/
+9
2019-11-17
In parse_isa_string, populate max_isa rather than state.misa
Andrew Waterman
1
-7
/
+3
2019-11-11
Revert "rvv: make vxrm/vxsat readable from FCSR"
Chih-Min Chao
1
-22
/
+5
2019-11-11
rvv: remove tail-zero
Chih-Min Chao
1
-4
/
+0
2019-10-30
rvv: remove dead code
Chih-Min Chao
1
-2
/
+0
2019-10-29
rvv: make vxrm/vxsat readable from FCSR
Chih-Min Chao
1
-5
/
+22
2019-10-29
rvv: fix marvelous vsetvlo again
Chih-Min Chao
1
-1
/
+1
2019-10-28
Initialize histogram_enabled and log_commits_enabled in constructor (#354)
Scott Johnson
1
-0
/
+1
2019-10-28
rvv: fix rs1 == 0 when vlmax is not reduced
Chih-Min Chao
1
-1
/
+3
2019-10-22
rvv: remove vmford
Chih-Min Chao
1
-6
/
+0
2019-10-15
rvv: add new rs1 = zero feature to vsetvl
Chih-Min Chao
1
-2
/
+13
2019-10-07
rvv: refine vill/vl handling for invalid case
Chih-Min Chao
1
-3
/
+5
2019-09-29
Adds --log-commits commandline option. (#323)
dave-estes-syzexion
1
-0
/
+13
2019-09-25
rvv:add t0/t1 to configure to setup default tailzero mode
Chih-Min Chao
1
-0
/
+4
2019-09-09
rvv: update missing inst in 1905 check
Chih-Min Chao
1
-0
/
+3
2019-09-04
rvv: add impl_table for instruction release check
Chih-Min Chao
1
-0
/
+769
2019-09-04
Remove statement with no effect
Andrew Waterman
1
-1
/
+0
2019-07-22
Set vtype.vill correctly; also reset it to true
Andrew Waterman
1
-3
/
+8
2019-07-22
Check presence of V extension when accessing vector CSRs
Andrew Waterman
1
-0
/
+15
2019-07-22
VL and VTYPE aren't writable CSRs
Andrew Waterman
1
-12
/
+0
2019-07-22
Writing non-existent CSRs, access FPRs with mstatus.FS=0 (#311)
Tim Newsome
1
-2
/
+7
2019-07-22
Add debug_mode state bit, rather than overloading dcsr.cause
Andrew Waterman
1
-4
/
+5
2019-07-22
Fix support for 32-bit hosts (but no V extension in that case!)
Andrew Waterman
1
-1
/
+5
2019-07-22
Support S-mode vectored interrupts
Andrew Waterman
1
-2
/
+3
2019-07-22
Fix clang uninitialized variable warning
Andrew Waterman
1
-1
/
+1
2019-06-12
rvv: merge the vcsr to ordinary csr and remove the redundant functions
Dave.Wen
1
-46
/
+31
2019-06-06
rvv: remove trailing space
Chih-Min Chao
1
-2
/
+2
2019-06-04
rvv: refine the code for checking the varch option set
Dave.Wen
1
-17
/
+13
2019-05-14
RV32Q is not invalid
Andrew Waterman
1
-6
/
+0
2019-05-14
Respect interrupt priorities even when not delegated
Andrew Waterman
1
-9
/
+13
2019-05-02
rvv: fix the spike isa option
Dave.Wen
1
-6
/
+0
2019-04-30
rvv: fixed type and removed redundant variable
Dave.Wen
1
-5
/
+3
2019-04-30
rvv: decouple the vectorUnit to the processor's state.
Dave.Wen
1
-8
/
+79
2019-04-30
rvv: add isa extension V
Dave
1
-1
/
+7
2019-04-22
fixed the wrong switch statement of set_vcsr
Dave.Wen
1
-33
/
+39
2019-04-20
improve the vectorUint_t
Dave
1
-4
/
+11
2019-04-18
fix the vsew decoding position
Dave.Wen
1
-1
/
+1
2019-04-18
rvv: support programming vcsr
Dave.Wen
1
-2
/
+27
2019-04-06
Fix use of old name `riscv-isa-run` (#269)
Luís Marques
1
-1
/
+1
2019-03-29
processor: for rounding mode and config access functions
Dave.Wen
1
-0
/
+8
2019-03-28
vsetvli: if rs1 = x0, then use maximum vector length
Dave.Wen
1
-3
/
+3
2019-03-27
rvv: add mlen for convenient
Chih-Min Chao
1
-0
/
+1
2019-03-27
add vmul, sbc, and shift instructions.
Dave.Wen
1
-0
/
+1
2019-03-04
reduce VLEN to 128 so multiple iterations are needed on the test data used fo...
Bruce Hoult
1
-1
/
+1
2019-02-24
Add comparison of user state (XPR, FPR, VPR) after each instruction
Bruce Hoult
1
-4
/
+1
2019-02-08
move vectorUnit_t::reset() and setVL() impl out of header
Bruce Hoult
1
-0
/
+26
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