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2022-10-04Silence unused-variable warnings in auto-generated codeAndrew Waterman1-0/+4
2022-10-04Suppress most unused variable warningsAndrew Waterman1-1/+1
2022-09-20Merge pull request #1036 from plctlab/plct-sscofpmf-devAndrew Waterman1-3/+16
add support for sscofpmf extension v0.5.2
2022-08-28Fix tval on illegal instruction faults with long illegal instructionYenHaoChen1-1/+4
The current spike implementation does not include the ILEN (maximum instruction length supported by the implementation), which is required to constrain the value of tval on an illegal instruction exception. Consider an implementation supporting only an RV64I base instruction set. The ILEN is 32 bits (spec sec. 1.5), and the MXLEN is 64 bits (spec sec. 5.1). Under an illegal instruction exception with the instruction longer than the ILEN, the mtval should contain the first ILEN (32 bits) of the faulting instruction. However, the current spike implementation lets the mtval be the instruction's first MXLEN (64 bits). To fix this bug, this PR masks out the upper bits of the tval and leaves the first ILEN bits of the faulting instruction. When this PR is being made, all official instructions are either 16 or 32 bits. So, We hard- code the ILEN to 32 bits.
2022-08-10Improve write log for vtype in set_vlWeiwei Li1-1/+2
Two writes to vtype will be logged in commitlog if vill is true
2022-08-10Fix code indentation in processor.cc, interactive.cc, debug_module.h/ccWeiwei Li1-1/+1
execute.cc, entropy_source.h and v_ext_macros.h
2022-08-09modify take_interrupt to support LCOFIP irqWeiwei Li1-0/+2
2022-08-09add support for sscofpmf extension v0.5.2Weiwei Li1-3/+14
since spike doesn't truly support counting of hardware performance events, only csr related read/write functions is supported currently
2022-08-08Merge pull request #1059 from plctlab/plct-stateen-fixAndrew Waterman1-1/+1
add stateen related check to frm/fflags
2022-08-03Add Sstc support. (#1057)i2h21-3/+20
2022-08-03add stateen related check to frm/fflags and then apply to fcsr implicitlyWeiwei Li1-1/+1
2022-07-21Merge pull request #1040 from plctlab/plct-priv-devAndrew Waterman1-5/+21
Update for counter related CSR
2022-07-21add support for time/timeh/htimedelta/htimedeltah csrsWeiwei Li1-0/+11
2022-07-21modify minstret/mcycle/minstreth/mcycleh to reuse rv32_low/high_csr_tWeiwei Li1-5/+10
2022-07-17add U mode check for *envcfg*Weiwei Li1-24/+26
- If U-mode is not supported, then registers menvcfg and menvcfgh do not exist - Since H extension requires S-mode, and S mode can not exsit without U-mode, so senvcfg, henvcfg/henvcfgh also do not exist if U-mode is not supported
2022-07-14add support for mconfigptr csr: it's hardwired to zero currentlyWeiwei Li1-1/+1
2022-07-14add support for m/henvcfgh csrsWeiwei Li1-3/+15
2022-07-13Properly log mstatush side effect updatesScott Johnson1-1/+2
These have never been logged properly.
2022-07-13Use rv32_low_csr_t for Smstateen CSRsScott Johnson1-2/+8
Otherwise they will have the same problem as #1044
2022-07-13Add proxy for accessing the low 32 bits of a 64-bit CSRScott Johnson1-1/+4
Use this for mstatus on RV32 so that `csrw mstatus` does not modify the bits in `mstatush`. Fixes #1044.
2022-07-13Remove unnecessary mask from rv32_high_csr_t constructorScott Johnson1-4/+3
2022-07-13Remove mstatush mask as unnecessaryScott Johnson1-1/+1
Mask in underlying CSR is sufficient. Mask field in rv32_high_csr_t is now unneeded and will be removed next.
2022-07-09add standalone class for fcsr and senvcfg csrWeiwei Li1-2/+2
2022-07-09add support for csrs of smstateen extensionsWeiwei Li1-0/+22
2022-07-07modify mstatush_csr_t to general rv32_high_csr_tWeiwei Li1-1/+5
2022-06-06Don't mask instruction bitsAndrew Waterman1-1/+1
No longer needed, since they are no longer sign-extended. Fixes #1022 by eliminating undefined behavior (64-bit instructions resulted in a shift amount equal to the datatype width).
2022-05-19Move ebreak* logic from take_trap into instructions. (#1006)Tim Newsome1-8/+0
Now that logic only affects ebreak instructions, and does not affect triggers that also cause a trap to be taken. Fixes #725. Although like Paul, I don't have a test for this case. Introduce trap_debug_mode so so ebreak instructions can force entry into debug mode.
2022-05-13Merge pull request #997 from riscv-software-src/simplify-decode_insnAndrew Waterman1-10/+13
Simplify decode_insn and insn_desc_t
2022-05-12Remove now-unnecessary null check from decode_insnAndrew Waterman1-2/+2
Fixes bug introduced in 5b7cdbe1cf75112bd2a472b7490b15fa7078d798
2022-05-12Assert that nullptrs can't make their way into the instructions listAndrew Waterman1-0/+2
2022-05-12Remove insn_func_t::supported fieldAndrew Waterman1-1/+0
The field is rendered unnecessary by 11f5942b7d8211e61b5ad9259d118033692c0759. Undoes some changes from 750f008e723bb3b20cec41a47ed5cec549447665.
2022-05-12Don't register instructions that aren't supportedAndrew Waterman1-8/+10
These add to the length of the instruction list without providing an apparent benefit.
2022-05-11Add PBMTE bit to menvcfg and henvcfg mask valuesRyan Buchner1-4/+8
Also make PBMTE set on reset for backward compatibility. Since before Spike proceeded as if these bits were set if the extension was enabled.
2022-05-11Change henvcfg csr to a henvcfg_csr_tRyan Buchner1-1/+1
To do so implemented henvcfg_csr_t. henvcfg.PBMTE will be read only 0 if menvcfg.PBMTE = 0.
2022-05-04Implement the new csr mseccfg for ePMP as dummysoberl@nvidia.com1-0/+2
2022-04-14add support for overlap instructionsWeiwei Li1-1/+8
* add DECLARE_OVERLAP_INSN to bind instructions with extension * add overlap_list.h to contain the declare of all overlapping instructions * make func function for overlapping instruction return NULL when the coresponding extension(s) is not supported.
2022-04-14fix style problems in decode.h and processor.ccWeiwei Li1-27/+30
2022-04-11Change processor_t to hold a pointer to an isa_parser_t (#973)Rupert Swarbrick1-11/+11
Before, it had another copy, which is a little unnecessary.
2022-04-11Merge pull request #944 from riscv-software-src/triggersScott Johnson1-12/+8
Refactor trigger code
2022-04-07Merge pull request #966 from riscv-software-src/fix-riscv-buildAndrew Waterman1-3/+3
Rename processor_t::set_csr to put_csr to fix build on RISC-V
2022-04-07Rename processor_t::set_csr to put_csr to fix build on RISC-VAndrew Waterman1-3/+3
The alternative would be to #undef set_csr after including encoding.h, but this solution strikes me as cleaner. Part of the reason is that set_csr was not a great name: it sounds like it implements the CSRRS (read & set) instruction, rather than impelementing a simple write.
2022-04-07Pass ref instead of pointer to trigger_updated()Tim Newsome1-2/+2
2022-04-06mmu: support asid/vmid (#928)Chih-Min Chao1-0/+3
The change makes [v]satp.asid and hgatp.vmid writtable and supports maximum length for rv32 and rv64. Software could write and read the satp.asid to get the valid length or check if the core supports asid/vmid or not. However, there is no official way to describe this hardware capability (device tree or something else). Two implementation flags are also added for future use and enabled by default. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2022-04-05Make triggers a vector of trigger_t.Tim Newsome1-1/+1
Not just mcontrol_t.
2022-04-05Abstract away access to load/store/execute bits.Tim Newsome1-3/+3
2022-04-05Make triggers::module_t::triggers private.Tim Newsome1-2/+2
2022-04-05Move num_triggers knowledge into triggers.hTim Newsome1-7/+5
2022-04-05Give triggers::module_t its own processor_t*Tim Newsome1-0/+1
2022-03-30Move tdata2 into mcontrol_tTim Newsome1-1/+1
2022-03-30Replace state.mcontrol with TM.triggers.Tim Newsome1-7/+4
Created a new triggers::module_t to hold the structure. Also make sure mcontrol_t instances are properly initialized.
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