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AgeCommit message (Expand)AuthorFilesLines
2022-10-04Silence unused-variable warnings in auto-generated codeAndrew Waterman1-0/+4
2022-10-04Suppress most unused variable warningsAndrew Waterman1-1/+1
2022-09-20Merge pull request #1036 from plctlab/plct-sscofpmf-devAndrew Waterman1-3/+16
2022-08-28Fix tval on illegal instruction faults with long illegal instructionYenHaoChen1-1/+4
2022-08-10Improve write log for vtype in set_vlWeiwei Li1-1/+2
2022-08-10Fix code indentation in processor.cc, interactive.cc, debug_module.h/ccWeiwei Li1-1/+1
2022-08-09modify take_interrupt to support LCOFIP irqWeiwei Li1-0/+2
2022-08-09add support for sscofpmf extension v0.5.2Weiwei Li1-3/+14
2022-08-08Merge pull request #1059 from plctlab/plct-stateen-fixAndrew Waterman1-1/+1
2022-08-03Add Sstc support. (#1057)i2h21-3/+20
2022-08-03add stateen related check to frm/fflags and then apply to fcsr implicitlyWeiwei Li1-1/+1
2022-07-21Merge pull request #1040 from plctlab/plct-priv-devAndrew Waterman1-5/+21
2022-07-21add support for time/timeh/htimedelta/htimedeltah csrsWeiwei Li1-0/+11
2022-07-21modify minstret/mcycle/minstreth/mcycleh to reuse rv32_low/high_csr_tWeiwei Li1-5/+10
2022-07-17add U mode check for *envcfg*Weiwei Li1-24/+26
2022-07-14add support for mconfigptr csr: it's hardwired to zero currentlyWeiwei Li1-1/+1
2022-07-14add support for m/henvcfgh csrsWeiwei Li1-3/+15
2022-07-13Properly log mstatush side effect updatesScott Johnson1-1/+2
2022-07-13Use rv32_low_csr_t for Smstateen CSRsScott Johnson1-2/+8
2022-07-13Add proxy for accessing the low 32 bits of a 64-bit CSRScott Johnson1-1/+4
2022-07-13Remove unnecessary mask from rv32_high_csr_t constructorScott Johnson1-4/+3
2022-07-13Remove mstatush mask as unnecessaryScott Johnson1-1/+1
2022-07-09add standalone class for fcsr and senvcfg csrWeiwei Li1-2/+2
2022-07-09add support for csrs of smstateen extensionsWeiwei Li1-0/+22
2022-07-07modify mstatush_csr_t to general rv32_high_csr_tWeiwei Li1-1/+5
2022-06-06Don't mask instruction bitsAndrew Waterman1-1/+1
2022-05-19Move ebreak* logic from take_trap into instructions. (#1006)Tim Newsome1-8/+0
2022-05-13Merge pull request #997 from riscv-software-src/simplify-decode_insnAndrew Waterman1-10/+13
2022-05-12Remove now-unnecessary null check from decode_insnAndrew Waterman1-2/+2
2022-05-12Assert that nullptrs can't make their way into the instructions listAndrew Waterman1-0/+2
2022-05-12Remove insn_func_t::supported fieldAndrew Waterman1-1/+0
2022-05-12Don't register instructions that aren't supportedAndrew Waterman1-8/+10
2022-05-11Add PBMTE bit to menvcfg and henvcfg mask valuesRyan Buchner1-4/+8
2022-05-11Change henvcfg csr to a henvcfg_csr_tRyan Buchner1-1/+1
2022-05-04Implement the new csr mseccfg for ePMP as dummysoberl@nvidia.com1-0/+2
2022-04-14add support for overlap instructionsWeiwei Li1-1/+8
2022-04-14fix style problems in decode.h and processor.ccWeiwei Li1-27/+30
2022-04-11Change processor_t to hold a pointer to an isa_parser_t (#973)Rupert Swarbrick1-11/+11
2022-04-11Merge pull request #944 from riscv-software-src/triggersScott Johnson1-12/+8
2022-04-07Merge pull request #966 from riscv-software-src/fix-riscv-buildAndrew Waterman1-3/+3
2022-04-07Rename processor_t::set_csr to put_csr to fix build on RISC-VAndrew Waterman1-3/+3
2022-04-07Pass ref instead of pointer to trigger_updated()Tim Newsome1-2/+2
2022-04-06mmu: support asid/vmid (#928)Chih-Min Chao1-0/+3
2022-04-05Make triggers a vector of trigger_t.Tim Newsome1-1/+1
2022-04-05Abstract away access to load/store/execute bits.Tim Newsome1-3/+3
2022-04-05Make triggers::module_t::triggers private.Tim Newsome1-2/+2
2022-04-05Move num_triggers knowledge into triggers.hTim Newsome1-7/+5
2022-04-05Give triggers::module_t its own processor_t*Tim Newsome1-0/+1
2022-03-30Move tdata2 into mcontrol_tTim Newsome1-1/+1
2022-03-30Replace state.mcontrol with TM.triggers.Tim Newsome1-7/+4
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