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AgeCommit message (Expand)AuthorFilesLines
2022-03-30Implement Sv57 and Sv57x4 translation modesAndrew Waterman1-0/+4
2022-03-30Refactor switch statement for DRY and readabilityAndrew Waterman1-6/+4
2022-03-29Split isa_parser_t out of processor.* and into its own file (#955)Rupert Swarbrick1-229/+0
2022-03-12Construct an isa_parser_t and pass it to processor_t constructorRupert Swarbrick1-11/+16
2022-03-11Incorporate supported privilege levels into isa_parser_t (#940)Rupert Swarbrick1-28/+24
2022-02-26add missed extensions specified by '--extension' to custom_extensionsWeiwei Li1-7/+10
2022-02-23perf: refine csr accessibility checkingChih-Min Chao1-9/+24
2022-02-18Split out MINSTRET and MCYCLERupert Swarbrick1-5/+5
2022-02-18Rename minstret CSR classes to something more generalRupert Swarbrick1-3/+3
2022-02-17Split Xbitmanip into its proposed component extensions (#918)Rupert Swarbrick1-1/+24
2022-02-16Merge branch 'plct-cmo-upstream' of https://github.com/plctlab/plct-spike int...Andrew Waterman1-0/+14
2022-02-04Don't require __int128 support in isa_parser_tAndrew Waterman1-5/+8
2022-01-29add isa string, csr support for cmo extensionsliweiwei1-0/+14
2022-01-27Bind disas for instructions with the isa supportWeiwei Li1-1/+1
2022-01-26Use unified ISA-string processing in spike-dasm and spikeWeiwei Li1-15/+13
2022-01-10Merge pull request #899 from riscv-software-src/rv32eAndrew Waterman1-24/+47
2022-01-09Changes to be cleaner wrt. -WextraAndrew Waterman1-0/+1
2022-01-06Support RV32E/RV64E base ISAsAndrew Waterman1-7/+13
2022-01-06Parse RV32E/RV64E base ISA strings; improve error messagesAndrew Waterman1-15/+30
2022-01-06DRY in illegal-instruction descriptorsAndrew Waterman1-2/+4
2022-01-06DRY in selecting instruction functionsAndrew Waterman1-3/+3
2021-12-07Add 'Zfhmin' extension (#880)Tsukasa #01 (a4lg)1-3/+5
2021-12-02Parse isa_string as C-style stringTsukasa OI1-2/+3
2021-12-02Use strtolower in parse_varch_stringTsukasa OI1-12/+9
2021-11-27Add comment that G implies Zicsr and ZifenceiAndrew Waterman1-1/+6
2021-11-27Accept dummy extension: "ZiHintPause"Tsukasa OI1-0/+2
2021-11-27Accept dummy extension: "Zifencei"Tsukasa OI1-0/+3
2021-11-13Use enum to specify the 3 options for masking of intr CSRsScott Johnson1-8/+4
2021-11-13Reformat code for narrower linesScott Johnson1-31/+39
2021-11-13Simplify calculation of VS-mode delegationScott Johnson1-2/+2
2021-11-13Mask hideleg by midelegScott Johnson1-1/+1
2021-11-13Mask hip and hie by midelegScott Johnson1-1/+1
2021-11-02Zbkx renames xperm.n and xperm.b as xperm4 and xperm8. (#846)Markku-Juhani O. Saarinen1-1/+1
2021-10-28Fix a link error when compiled without optimization option "-O2" (#844)eric-xtang10081-0/+2
2021-10-14Split 'P' to EXT_ZPN and friends (#830)marcfedorow1-0/+6
2021-10-06Make vxsat into its own classScott Johnson1-1/+1
2021-10-04Fix VSIE CSR write emulation (#822)Anup Patel1-1/+1
2021-09-30Use more conservative and realistic default for vstart_aluAndrew Waterman1-1/+1
2021-09-30Remove vestiges of legacy RVV SLEN parameterAndrew Waterman1-9/+1
2021-09-29Remove no-longer-needed code for CSR reads/writesScott Johnson1-43/+0
2021-09-29Correction to address of FCSRScott Johnson1-1/+1
2021-09-29Convert vcsr to csr_tScott Johnson1-18/+2
2021-09-29Convert vlenb to csr_tScott Johnson1-5/+1
2021-09-29Convert vtype to csr_tScott Johnson1-9/+5
2021-09-29Convert vl to csr_tScott Johnson1-10/+6
2021-09-29Convert vxrm to csr_tScott Johnson1-23/+3
2021-09-29Convert vstart to csr_tScott Johnson1-14/+2
2021-09-29Convert vxsat to csr_tScott Johnson1-15/+5
2021-09-28Convert mhartid to csr_tScott Johnson1-1/+1
2021-09-28Convert mvendorid to csr_tScott Johnson1-1/+1
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