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AgeCommit message (Expand)AuthorFilesLines
2016-06-08Add degenerate HW breakpoint implementationAndrew Waterman1-0/+4
2016-05-23Turn off debugging.Tim Newsome1-1/+0
2016-05-23Tell gdb we can handle large packets.Tim Newsome1-1/+1
2016-05-23Exceptions in Debug Mode don't update any regs.Tim Newsome1-7/+7
2016-05-23Remove already-implemented TODO.Tim Newsome1-1/+0
2016-05-23Implement ebreak[mhsu].Tim Newsome1-2/+5
2016-05-23Remove dependency on include file in my homedir.Tim Newsome1-31/+32
2016-05-23Make -H halt the core right out of reset.Tim Newsome1-2/+5
2016-05-23Halt when gdb user hits ^C.Tim Newsome1-1/+0
2016-05-23Single step appears to work.Tim Newsome1-0/+1
2016-05-23Fix off-by-two in general read registers.Tim Newsome1-1/+0
2016-05-23Remove unused code.Tim Newsome1-1/+2
2016-05-23Add dret.Tim Newsome1-1/+1
2016-05-23Implement single memory read access.Tim Newsome1-1/+5
2016-05-23Exceptions in Debug Mode, stay in Debug Mode.Tim Newsome1-1/+5
2016-05-23Continue works well enough for DebugTest.test_exitTim Newsome1-1/+0
2016-05-23Refactor how we track in-progress operations.Tim Newsome1-1/+5
2016-05-23processor_t unfriends gdbserver_t.Tim Newsome1-2/+2
2016-05-23Add debug_module bus device.Tim Newsome1-6/+2
2016-05-23Can jump to and execute Debug ROM.Tim Newsome1-1/+6
2016-05-23When gdb connects, jump to Debug ROM and segfault.Tim Newsome1-0/+5
2016-05-23Gutting direct-access gdb.Tim Newsome1-13/+9
2016-05-23Add writing to DCSR, DPC, DSCRATCH.Tim Newsome1-0/+37
2016-05-23Only halt on ebreak if a debugger is attached.Tim Newsome1-2/+2
2016-05-23Flush icache when using swbps and report to gdb.Tim Newsome1-2/+3
2016-05-23Software breakpoints seem to work.Tim Newsome1-0/+6
2016-05-23Looks like single step works.Tim Newsome1-1/+6
2016-05-23Now you can halt/continue from gdb.Tim Newsome1-1/+6
2016-05-22Allow delegation of device interruptsAndrew Waterman1-1/+1
2016-05-02Add back IPI supportAndrew Waterman1-14/+11
2016-05-02Remove MIPI; mip.MSIP bit is read-onlyAndrew Waterman1-6/+2
2016-05-02Remove tohost/fromhost registersAndrew Waterman1-14/+0
2016-04-30Initialize mtvec to DEFAULT_MTVECAndrew Waterman1-0/+1
2016-04-30Remove SCRs; add padding after config stringAndrew Waterman1-1/+0
2016-04-29Move much closer to new platform-M memory mapAndrew Waterman1-4/+5
2016-04-28Remove MTIME[CMP]; add RTC deviceAndrew Waterman1-16/+1
2016-04-06Remove non-standard uarch CSRsAndrew Waterman1-17/+0
2016-03-16Update definition of base field in misa registerAndrew Waterman1-6/+1
2016-03-03Fix up interrupt delegationAndrew Waterman1-25/+21
2016-03-02Add counter-enable registersAndrew Waterman1-0/+32
2016-03-02WIP on priv spec v1.9Andrew Waterman1-60/+6
2016-03-02New definitions of misa/marchid/mvendoridAndrew Waterman1-8/+19
2016-03-02implement PUM functionalityAndrew Waterman1-5/+7
2016-03-02sptbr now a holds a PPN, not an addressAndrew Waterman1-1/+1
2016-03-02Use simpler MTVEC schemeAndrew Waterman1-2/+2
2016-03-02Zero-extend all CSR writesAndrew Waterman1-3/+4
2016-03-02Fix ERET serialization strategyAndrew Waterman1-0/+2
2016-03-02WIP on priv spec v1.9Andrew Waterman1-89/+101
2016-01-12don't ignore data value when writing MIPIAndrew Waterman1-1/+1
2015-11-12Generate device tree for target machineAndrew Waterman1-23/+49