Age | Commit message (Collapse) | Author | Files | Lines | |
---|---|---|---|---|---|
2014-12-04 | Support 2/4/6/8-byte instructions | Andrew Waterman | 1 | -9/+9 | |
Most of the complexity is in instruction address translation, since instructions may span page boundaries. | |||||
2014-11-30 | Implement timer faithfully | Andrew Waterman | 1 | -46/+64 | |
rdcycle/rdinstret now have single-instruction granularity. Questionable behavior when timer interrupts occurred around the same time as the compare register is written should be fixed. | |||||
2014-08-15 | Added PC histogram option. | Christopher Celio | 1 | -0/+24 | |
- Spits out all PCs (on 4B granularity) executed with count. - Requires a compile time configuration option. - Also requires a run-time flag. | |||||
2014-08-07 | Support uarch counters (degenerately) | Andrew Waterman | 1 | -0/+17 | |
2014-07-08 | Disallow access to FCSR when FP is disabled | Andrew Waterman | 1 | -0/+6 | |
2014-07-07 | Minor refactoring | Andrew Waterman | 1 | -13/+13 | |
2014-06-13 | Commit log now prints while interrupts are enabled. | Christopher Celio | 1 | -8/+15 | |
- Previous behavior was to print the commit log only in user code. | |||||
2014-06-13 | Only print commit log if instruction commits | Andrew Waterman | 1 | -3/+9 | |
2014-06-12 | Set status.u64 to true on boot | Andrew Waterman | 1 | -1/+1 | |
This isn't required by the ISA but it matches existing HW. | |||||
2014-03-18 | Support RV32 RDTIMEH/RDCYCLEH/RDINSTRETH | Andrew Waterman | 1 | -5/+11 | |
2014-03-15 | speed up compilation a bit | Andrew Waterman | 1 | -0/+1 | |
2014-02-13 | Fix I$ simulator not making forward progress | Andrew Waterman | 1 | -16/+12 | |
2014-02-12 | Fix commit log when !debug | Andrew Waterman | 1 | -25/+15 | |
2014-02-07 | Clear EVEC LSBs, which kindly prevents a segfault | Andrew Waterman | 1 | -2/+2 | |
2014-01-24 | Handle CSR permissions correctly | Andrew Waterman | 1 | -1/+4 | |
2014-01-16 | Initialize tohost and fromhost to zero | Andrew Waterman | 1 | -2/+5 | |
Surprising we got away without doing this for so long | |||||
2014-01-13 | Improve performance for branchy code | Andrew Waterman | 1 | -31/+56 | |
We now use a heavily unrolled loop as the software I$, which allows the host machine's branch target prediction to associate target PCs with unique-ish host PCs. | |||||
2013-12-17 | Speed things up quite a bit | Andrew Waterman | 1 | -26/+50 | |
2013-11-25 | Update to new privileged ISA | Andrew Waterman | 1 | -46/+61 | |
2013-10-18 | clean up SR_EA, the enable accelerator bit in status reg | Yunsup Lee | 1 | -3/+2 | |
2013-10-18 | refactor disassembler, and add hwacha disassembler | Yunsup Lee | 1 | -11/+19 | |
2013-10-16 | fix missing null check when there's no extension | Yunsup Lee | 1 | -1/+2 | |
2013-10-15 | Propogate the reset call to the extensions as well. Add reset function to ↵ | Stephen Twigg | 1 | -1/+2 | |
extensions (demonstration in dummy acc) | |||||
2013-09-27 | Added commit logging (--enable-commitlog). Also fixed disasm bug. | Christopher Celio | 1 | -0/+16 | |
2013-09-23 | fixes compile bug for not being able to find std::logic_error | Scott Beamer | 1 | -0/+1 | |
2013-09-11 | Implement zany immediates | Andrew Waterman | 1 | -6/+6 | |
2013-08-18 | Renumber PCRs | Andrew Waterman | 1 | -4/+4 | |
2013-08-13 | Implement RoCC and add a dummy RoCC | Andrew Waterman | 1 | -27/+29 | |
Enable it with --extension=dummy | |||||
2013-08-11 | Instructions are no longer member functions | Andrew Waterman | 1 | -83/+98 | |
2013-07-26 | New supervisor mode | Andrew Waterman | 1 | -6/+9 | |
2013-07-26 | Remove more vector stuff | Andrew Waterman | 1 | -49/+2 | |
2013-07-26 | Rip out Hwacha for now | Andrew Waterman | 1 | -8/+0 | |
2013-07-26 | Rip out RVC for now | Andrew Waterman | 1 | -1/+1 | |
2013-07-26 | Generate instruction decoder dynamically | Andrew Waterman | 1 | -3/+48 | |
This will make it easier for accelerators to add instructions. | |||||
2013-07-22 | Add xspike program | Andrew Waterman | 1 | -6/+6 | |
2013-04-25 | use inttypes macros to print uint64_t | Andrew Waterman | 1 | -7/+8 | |
2013-04-24 | fixes to correctly simulate the vector unit | Yunsup Lee | 1 | -0/+2 | |
2013-03-29 | add load-reserved/store-conditional instructions | Andrew Waterman | 1 | -3/+0 | |
2013-03-29 | ignore writes to SR IP field | Andrew Waterman | 1 | -2/+3 | |
2013-03-25 | add BSD license | Andrew Waterman | 1 | -0/+2 | |
2013-03-25 | truncate effective addresses in rv32 | Andrew Waterman | 1 | -2/+1 | |
also, employ a more efficient instruction dispatch based upon rv32 mode. | |||||
2013-03-25 | expose pending interrupts in status register | Andrew Waterman | 1 | -7/+14 | |
2013-02-13 | clean up fetch-execute loop a bit | Andrew Waterman | 1 | -12/+4 | |
2012-11-13 | fix vector code simulation problem, turn on SR_U64 | Yunsup Lee | 1 | -1/+1 | |
2012-08-30 | new tohost/fromhost semantics | Andrew Waterman | 1 | -1/+2 | |
2012-08-01 | new tohost/fromhost semantics | Andrew Waterman | 1 | -2/+0 | |
2012-07-22 | correct HTIF reset behavior | Andrew Waterman | 1 | -17/+12 | |
cores' reset signals can be independently toggled | |||||
2012-05-09 | per-core tohost/fromhost registers | Andrew Waterman | 1 | -7/+22 | |
update your fesvr | |||||
2012-03-24 | new supervisor mode | Andrew Waterman | 1 | -34/+114 | |
2012-03-19 | abstract regfile behind object | Andrew Waterman | 1 | -2/+2 | |