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AgeCommit message (Expand)AuthorFilesLines
2014-12-04Support 2/4/6/8-byte instructionsAndrew Waterman1-9/+9
2014-11-30Implement timer faithfullyAndrew Waterman1-46/+64
2014-08-15Added PC histogram option.Christopher Celio1-0/+24
2014-08-07Support uarch counters (degenerately)Andrew Waterman1-0/+17
2014-07-08Disallow access to FCSR when FP is disabledAndrew Waterman1-0/+6
2014-07-07Minor refactoringAndrew Waterman1-13/+13
2014-06-13Commit log now prints while interrupts are enabled.Christopher Celio1-8/+15
2014-06-13Only print commit log if instruction commitsAndrew Waterman1-3/+9
2014-06-12Set status.u64 to true on bootAndrew Waterman1-1/+1
2014-03-18Support RV32 RDTIMEH/RDCYCLEH/RDINSTRETHAndrew Waterman1-5/+11
2014-03-15speed up compilation a bitAndrew Waterman1-0/+1
2014-02-13Fix I$ simulator not making forward progressAndrew Waterman1-16/+12
2014-02-12Fix commit log when !debugAndrew Waterman1-25/+15
2014-02-07Clear EVEC LSBs, which kindly prevents a segfaultAndrew Waterman1-2/+2
2014-01-24Handle CSR permissions correctlyAndrew Waterman1-1/+4
2014-01-16Initialize tohost and fromhost to zeroAndrew Waterman1-2/+5
2014-01-13Improve performance for branchy codeAndrew Waterman1-31/+56
2013-12-17Speed things up quite a bitAndrew Waterman1-26/+50
2013-11-25Update to new privileged ISAAndrew Waterman1-46/+61
2013-10-18clean up SR_EA, the enable accelerator bit in status regYunsup Lee1-3/+2
2013-10-18refactor disassembler, and add hwacha disassemblerYunsup Lee1-11/+19
2013-10-16fix missing null check when there's no extensionYunsup Lee1-1/+2
2013-10-15Propogate the reset call to the extensions as well. Add reset function to ext...Stephen Twigg1-1/+2
2013-09-27Added commit logging (--enable-commitlog). Also fixed disasm bug.Christopher Celio1-0/+16
2013-09-23fixes compile bug for not being able to find std::logic_errorScott Beamer1-0/+1
2013-09-11Implement zany immediatesAndrew Waterman1-6/+6
2013-08-18Renumber PCRsAndrew Waterman1-4/+4
2013-08-13Implement RoCC and add a dummy RoCCAndrew Waterman1-27/+29
2013-08-11Instructions are no longer member functionsAndrew Waterman1-83/+98
2013-07-26New supervisor modeAndrew Waterman1-6/+9
2013-07-26Remove more vector stuffAndrew Waterman1-49/+2
2013-07-26Rip out Hwacha for nowAndrew Waterman1-8/+0
2013-07-26Rip out RVC for nowAndrew Waterman1-1/+1
2013-07-26Generate instruction decoder dynamicallyAndrew Waterman1-3/+48
2013-07-22Add xspike programAndrew Waterman1-6/+6
2013-04-25use inttypes macros to print uint64_tAndrew Waterman1-7/+8
2013-04-24fixes to correctly simulate the vector unitYunsup Lee1-0/+2
2013-03-29add load-reserved/store-conditional instructionsAndrew Waterman1-3/+0
2013-03-29ignore writes to SR IP fieldAndrew Waterman1-2/+3
2013-03-25add BSD licenseAndrew Waterman1-0/+2
2013-03-25truncate effective addresses in rv32Andrew Waterman1-2/+1
2013-03-25expose pending interrupts in status registerAndrew Waterman1-7/+14
2013-02-13clean up fetch-execute loop a bitAndrew Waterman1-12/+4
2012-11-13fix vector code simulation problem, turn on SR_U64Yunsup Lee1-1/+1
2012-08-30new tohost/fromhost semanticsAndrew Waterman1-1/+2
2012-08-01new tohost/fromhost semanticsAndrew Waterman1-2/+0
2012-07-22correct HTIF reset behaviorAndrew Waterman1-17/+12
2012-05-09per-core tohost/fromhost registersAndrew Waterman1-7/+22
2012-03-24new supervisor modeAndrew Waterman1-34/+114
2012-03-19abstract regfile behind objectAndrew Waterman1-2/+2
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