aboutsummaryrefslogtreecommitdiff
path: root/riscv/processor.cc
AgeCommit message (Expand)AuthorFilesLines
2011-12-10fix utidx assign bug, make ut code execute fasterYunsup Lee1-1/+2
2011-11-11Remove dependence on binutilsYour Name1-23/+5
2011-11-11Use new compiler toolchain's disassemblerAndrew Waterman1-3/+5
2011-11-11Changed supervisor modeAndrew Waterman1-9/+14
2011-06-19temporary undoing of renamingAndrew Waterman1-0/+240
2011-06-12[sim] renamed to riscv-isa-runAndrew Waterman1-273/+0
2011-06-12[xcc] minor performance tweaksAndrew Waterman1-4/+10
2011-06-11[xcc] fixed simulator build timeAndrew Waterman1-52/+0
2011-06-11[xcc] cleaned up mmu codeAndrew Waterman1-3/+3
2011-06-10[sim, opcodes] made sim more decoupled from opcodesAndrew Waterman1-3/+53
2011-05-31[sim] minor sim cleanupAndrew Waterman1-2/+2
2011-05-29[sim,opcodes] improved sim build and run performanceAndrew Waterman1-27/+48
2011-05-28[fesvr,xcc,sim] fixed multicore sim for akarosAndrew Waterman1-30/+48
2011-05-23[sim,xcc] add rdcycle/rdtime/rdinstretAndrew Waterman1-2/+2
2011-05-19[sim] change default hwvlYunsup Lee1-3/+3
2011-05-19[sim] vlen calc reflects the hardwareYunsup Lee1-9/+6
2011-05-16[sim,pk] cleanups & initial virtual memory supportAndrew Waterman1-0/+1
2011-05-13[sim] initial support for virtual memoryAndrew Waterman1-0/+3
2011-04-30[sim] hacked in a dcache simulatorAndrew Waterman1-5/+29
2011-04-15[sim] added icache simulator (disabled by default)Andrew Waterman1-2/+18
2011-04-11[xcc,sim,opcodes] more rvc instructions and bug fixesAndrew Waterman1-1/+2
2011-04-09[sim] add disable option for vectorYunsup Lee1-0/+3
2011-04-09[sim] set SR_EV for utsYunsup Lee1-0/+1
2011-04-09[sim] add vt stuffYunsup Lee1-1/+43
2011-04-09[sim,pk] reorganized status registerAndrew Waterman1-3/+3
2011-04-09[xcc,pk,sim,opcodes] added first RVC instructionAndrew Waterman1-3/+6
2011-03-25[xcc,pk,opcodes,sim] updated encoding/insn namesAndrew Waterman1-0/+2
2011-02-04[sim,pk] added interrupt-pending field to cause regAndrew Waterman1-10/+6
2011-01-18[opcodes, sim, xcc] made *w insns illegal in RV32Andrew Waterman1-10/+12
2010-11-21[opcodes, pk, sim, xcc] Tweaked FP encodingAndrew Waterman1-1/+0
2010-10-26[pk,sim,xcc] get rid of at register, introduce tp registerYunsup Lee1-1/+0
2010-10-15[pk, sim] added FPU emulation support to proxy kernelAndrew Waterman1-0/+2
2010-10-05[xcc,sim] eliminated vectored trapsAndrew Waterman1-2/+4
2010-09-09Merge branch 'master' of /project/eecs/parlab/git/projects/riscvAndrew Waterman1-0/+2
2010-09-09[pk, sim] added interrupt support to sim; added timer interruptAndrew Waterman1-4/+17
2010-09-08[sim] add while to interactive_untilYunsup Lee1-0/+2
2010-09-07[sim] fix stdint.h __STDC_LIMIT_MACROS problemYunsup Lee1-1/+1
2010-09-07[sim, xcc] branches now have 2-byte-aligned displacementsAndrew Waterman1-0/+2
2010-09-06[sim, xcc] bthread threading model exposed; insn encoding cleaned upAndrew Waterman1-0/+1
2010-08-24[xcc] argc/argv work for 32b programsAndrew Waterman1-1/+0
2010-08-24[sim] privileged mode support for 32-bit operationAndrew Waterman1-6/+8
2010-08-09[xcc,sim] implement FP using softfloatAndrew Waterman1-0/+8
2010-08-04[xcc,pk,sim] Added first part of FP supportAndrew Waterman1-0/+6
2010-07-28[sim,xcc] Changed instruction format to RISC-VAndrew Waterman1-2/+3
2010-07-21[pk,sim] first cut of appserver communication linkAndrew Waterman1-2/+8
2010-07-18Reorganized directory structureAndrew Waterman1-0/+97
generated by cgit v1.1 at 2024-08-16 12:17:38 +0000