| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2019-11-27 | rvv: change vsetvl[i] to match 0.8 spec | Chih-Min Chao | 1 | -1/+1 |
| 2019-07-22 | Check vtype.vill for all vector instructions except vsetvl[i] | Andrew Waterman | 1 | -0/+1 |
| 2019-06-03 | rvv: refactor to the VU | Dave.Wen | 1 | -1/+1 |
| 2019-05-09 | vsetvl: double set vl may cause error. Need to be fixed later | Dave.Wen | 1 | -3/+1 |
| 2019-05-07 | vsetvl[i]: if vl == 0, don't update the destination | Dave.Wen | 1 | -1/+3 |
| 2019-04-30 | rvv: decouple the vectorUnit to the processor's state. | Dave.Wen | 1 | -1/+1 |
| 2019-04-20 | update the setVL naming to set_vl | Dave | 1 | -1/+1 |
| 2019-04-18 | rvv: add vsetvl | Dave | 1 | -0/+1 |
| 2013-07-26 | Rip out Hwacha for now | Andrew Waterman | 1 | -3/+0 |
| 2011-06-19 | temporary undoing of renaming | Andrew Waterman | 1 | -0/+3 |
| 2011-06-12 | [sim] renamed to riscv-isa-run | Andrew Waterman | 1 | -3/+0 |
| 2011-05-15 | [libs,opcodes,pk,sim,xcc] add mov*,fmov*, shuffle vec insts | Yunsup Lee | 1 | -0/+3 |
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index : rocket-tools/riscv-gnu-toolchain/spike.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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