| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2022-09-08 | Remove unnecessary argument alu(always false) from macro | Weiwei Li | 1 | -1/+1 |
| 2020-08-03 | rvv: add 'vstartalu" option to --varch arugment | Chih-Min Chao | 1 | -1/+1 |
| 2020-05-28 | rvv: wrap align and overlap checking macro | Chih-Min Chao | 1 | -1/+1 |
| 2019-12-20 | rvv: change vsetvl[i] to match 0.8 spec | Chih-Min Chao | 1 | -1/+1 |
| 2019-07-19 | Check vtype.vill for all vector instructions except vsetvl[i] | Andrew Waterman | 1 | -0/+1 |
| 2019-06-18 | rvv: add control instructions and system register access | Chih-Min Chao | 1 | -0/+1 |
| 2013-07-26 | Rip out Hwacha for now | Andrew Waterman | 1 | -3/+0 |
| 2011-06-19 | temporary undoing of renaming | Andrew Waterman | 1 | -0/+3 |
| 2011-06-12 | [sim] renamed to riscv-isa-run | Andrew Waterman | 1 | -3/+0 |
| 2011-05-15 | [libs,opcodes,pk,sim,xcc] add mov*,fmov*, shuffle vec insts | Yunsup Lee | 1 | -0/+3 |
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index : rocket-tools/riscv-gnu-toolchain/spike.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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