rocket-tools/riscv-gnu-toolchain/spike.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2020-03-11	commitlog: fix missing dump for some instructions	Chih-Min Chao	1	-4/+4
2020-02-13	rvv: reset vstart to 0 when vmv.s.x and vmv.x.s and also check the vstart < v...	Dave.Wen	1	-1/+3
2019-11-11	rvv: remove tail-zero	Chih-Min Chao	1	-20/+0
2019-09-25	rvv: use new state to support runtime tz change	Chih-Min Chao	1	-1/+1
2019-09-25	rvv: fix vmv non-tail-zero issue	Chih-Min Chao	1	-15/+17
2019-07-22	Check vtype.vill for all vector instructions except vsetvl[i]	Andrew Waterman	1	-0/+1
2019-06-08	rvv: reformat the code by 'astyle insns/v*.h -s2 -A2'	Dave	1	-1/+1
2019-06-03	rvv: refactor to the VU	Dave.Wen	1	-13/+13
2019-06-02	rvv: spec update	Dave.Wen	1	-0/+1
2019-04-30	rvv: decouple the vectorUnit to the processor's state.	Dave.Wen	1	-13/+13
2019-04-24	rvv: vmv.s.x reset vl after operation	Chih-Min Chao	1	-2/+5
2019-04-24	rvv: fix vmv.s.x and vfmv.s.f	Chih-Min Chao	1	-3/+1
2019-04-18	rvv: fix vmv.s.x wordaround	Chih-Min Chao	1	-6/+4
2019-04-15	fix vmv.s.x, it set other part as 0	Chih-Min Chao	1	-8/+31
2019-04-15	wt: fix: temporary use rs2 register	Chih-Min Chao	1	-4/+21
2019-04-08	fixed: xext, vmulh[u]_v[vx], vsne_vi	Dave.Wen	1	-3/+4
2019-03-28	rvv: add vmv_s_x	Dave.Wen	1	-5/+4
2019-03-26	update all instruction templates and part of the implementations	Dave.Wen	1	-1/+1
2019-03-26	declare vector instructions without VFUNARY0/1 and VMUNARY0	Dave.Wen	1	-0/+5