| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2013-11-25 | Update to new privileged ISA | Andrew Waterman | 1 | -2/+0 |
| 2013-09-27 | Use WRITE_RD/WRITE_FRD macros to write registers | Andrew Waterman | 1 | -1/+1 |
| 2013-09-11 | Implement zany immediates | Andrew Waterman | 1 | -1/+1 |
| 2013-08-11 | Instructions are no longer member functions | Andrew Waterman | 1 | -3/+1 |
| 2012-08-30 | new tohost/fromhost semantics | Andrew Waterman | 1 | -2/+1 |
| 2012-08-01 | new tohost/fromhost semantics | Andrew Waterman | 1 | -1/+2 |
| 2012-03-24 | new supervisor mode | Andrew Waterman | 1 | -46/+3 |
| 2011-11-11 | Changed supervisor mode | Andrew Waterman | 1 | -12/+14 |
| 2011-06-19 | temporary undoing of renaming | Andrew Waterman | 1 | -0/+45 |
| 2011-06-12 | [sim] renamed to riscv-isa-run | Andrew Waterman | 1 | -46/+0 |
| 2011-05-28 | [fesvr,xcc,sim] fixed multicore sim for akaros | Andrew Waterman | 1 | -0/+4 |
| 2011-05-18 | [opcodes,pk,sim] add more vector traps (for #banks, illegal instructions) | Yunsup Lee | 1 | -0/+5 |
| 2011-05-16 | [sim,pk] cleanups & initial virtual memory support | Andrew Waterman | 1 | -0/+4 |
| 2011-02-04 | [sim,pk] added interrupt-pending field to cause reg | Andrew Waterman | 1 | -1/+1 |
| 2010-10-05 | [xcc,sim] eliminated vectored traps | Andrew Waterman | 1 | -1/+1 |
| 2010-09-20 | [xcc, sim] changed instruction format so imm12 subs for rs2 | Andrew Waterman | 1 | -10/+10 |
| 2010-09-09 | Merge branch 'master' of /project/eecs/parlab/git/projects/riscv | Andrew Waterman | 1 | -0/+1 |
| 2010-09-09 | [pk, sim] added interrupt support to sim; added timer interrupt | Andrew Waterman | 1 | -8/+13 |
| 2010-09-08 | [sim] add while to interactive_until | Yunsup Lee | 1 | -1/+2 |
| 2010-09-06 | [sim, xcc] added PCRs to replace k0 and k1 | Andrew Waterman | 1 | -0/+7 |
| 2010-08-24 | [sim] privileged mode support for 32-bit operation | Andrew Waterman | 1 | -5/+6 |
| 2010-08-03 | [pk,sim,xcc] Renamed instructions to RISC-V spec | Andrew Waterman | 1 | -0/+19 |
