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execute.cc
Age
Commit message (
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Author
Files
Lines
2020-05-19
rvv: store eew and emul to P.VU for unit/stride load/store
Chih-Min Chao
1
-1
/
+1
2020-05-13
rvv: fractional_lmul when lmul < 1
Dave.Wen
1
-4
/
+5
2020-05-13
vtype: fix the vta and vma functions and debugging display
Dave.Wen
1
-2
/
+2
2020-05-13
eew: fix the eew=0 case
Dave.Wen
1
-0
/
+2
2020-04-05
Write execution logs to a named log file (#409)
Rupert Swarbrick
1
-27
/
+37
2020-03-16
commitlog: fix build failed
Chih-Min Chao
1
-4
/
+6
2020-03-16
commitlog: fix wrong dump when exception occur
Chih-Min Chao
1
-3
/
+8
2020-03-03
commitlog: enhance vector dump
Chih-Min Chao
1
-5
/
+14
2020-02-19
commitlog: print vsew in bit
Chih-Min Chao
1
-1
/
+1
2020-02-12
debug: refine per-inst difference record
Chih-Min Chao
1
-3
/
+3
2020-02-12
commitlog: fix printf format warning
Chih-Min Chao
1
-1
/
+1
2020-02-12
commitlog: extend reg record to keep multiple accesss
Chih-Min Chao
1
-15
/
+55
2020-02-12
commitlog: extend load/store record to keep multiple access
Chih-Min Chao
1
-7
/
+9
2019-12-19
extend the commit and memory writes log feature with memory reads (#370)
John Ingalls
1
-5
/
+11
2019-09-29
Extends the commit log feature with memory writes. (#324)
dave-estes-syzexion
1
-5
/
+14
2019-09-29
Adds --log-commits commandline option. (#323)
dave-estes-syzexion
1
-1
/
+3
2019-07-22
Add debug_mode state bit, rather than overloading dcsr.cause
Andrew Waterman
1
-3
/
+3
2019-06-12
rvv: revert the debug information
Dave.Wen
1
-1
/
+17
2019-06-12
WIP: move from gamma07 to gamma03
Dave.Wen
1
-17
/
+2
2019-05-14
Implement debug hasel support (#287)
Tim Newsome
1
-7
/
+10
2019-04-30
rvv: decouple the vectorUnit to the processor's state.
Dave.Wen
1
-10
/
+10
2019-04-15
rvv: refine vector register expression in interactive mode
Chih-Min Chao
1
-1
/
+2
2019-03-27
rvv: fix compiler warning
Chih-Min Chao
1
-1
/
+1
2019-02-24
Add comparison of user state (XPR, FPR, VPR) after each instruction
Bruce Hoult
1
-0
/
+63
2018-08-10
Fix 2 trigger corner cases. (#229)
Tim Newsome
1
-3
/
+5
2018-04-30
Fix commit log for serializing instructions
Andrew Waterman
1
-1
/
+1
2018-04-30
Only break out of the simulator loop on WFI, not on CSR writes
Andrew Waterman
1
-1
/
+2
2018-03-21
Implement Hauser misa.C misalignment proposal (#187)
Andrew Waterman
1
-1
/
+0
2018-03-09
Fix single stepping csrrw instructions (#178)
Tim Newsome
1
-8
/
+7
2018-03-06
Narrow the interface used by the processors and memory to the top-level simul...
Prashanth Mundkur
1
-1
/
+0
2018-03-03
Implement clearing-misa.C-while-PC-is-misaligned proposal
Andrew Waterman
1
-0
/
+1
2018-02-21
Don't allow 32-bit instructions to take up multiple slots in I$
Andrew Waterman
1
-16
/
+2
2017-12-11
Make progbuf a run-time option.
Tim Newsome
1
-3
/
+1
2017-11-20
Fix commitlog. (#162)
Christopher Celio
1
-5
/
+8
2017-10-20
Fix commit-log for Q extension, and for RV32 (#143)
Andrew Waterman
1
-15
/
+42
2017-09-21
Fix comment typo. (#126)
Tim Newsome
1
-1
/
+1
2017-04-18
debug: Checkpoint which somewhat works with OpenOCD v13, but still has some b...
Megan Wachs
1
-5
/
+8
2017-04-17
Merge remote-tracking branch 'origin/priv-1.10' into HEAD
Megan Wachs
1
-2
/
+2
2017-02-23
Implement halt request.
Tim Newsome
1
-2
/
+1
2017-02-21
Don't waste time spinning in place in debug mode
Tim Newsome
1
-4
/
+7
2017-02-20
serialize simulator on wfi
Andrew Waterman
1
-1
/
+1
2017-02-02
Fix interrupt delegation for coprocessors
Andrew Waterman
1
-1
/
+1
2016-12-15
Fix single stepping over faulting instructions. (#80)
Tim Newsome
1
-0
/
+5
2016-12-01
Added comments about the modified Duff's Device in execute.cc (#77)
Andy Wright
1
-0
/
+37
2016-08-25
partially update spike to newer debug spec
Andrew Waterman
1
-2
/
+6
2016-08-25
Fix spike interactive (-d) mode
Andrew Waterman
1
-5
/
+3
2016-08-22
Implement address and data triggers.
Tim Newsome
1
-2
/
+32
2016-07-13
Fix single step over csrw instructions. (#57)
Tim Newsome
1
-5
/
+9
2016-05-23
Remove obsolete TODO.
Tim Newsome
1
-3
/
+0
2016-05-23
Make -H halt the core right out of reset.
Tim Newsome
1
-7
/
+8
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