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2022-10-06Don't use reexecution as the means to implement trigger-afterAndrew Waterman1-9/+0
The scheme was based on the notion that memory accesses are idempotent up until the point the trigger would've been hit, which isn't true in the case of side-effecting loads and data-value triggers. Instead, check the trigger on the next instruction fetch. To keep the perf overhead minimal, perform this check on the I$ refill path, and ensure that path is taken by flushing the I$.
2022-10-04Suppress most unused variable warningsAndrew Waterman1-1/+1
2022-10-04Delete functions that are actually unusedAndrew Waterman1-4/+0
2022-08-10Fix code indentation in processor.cc, interactive.cc, debug_module.h/ccWeiwei Li1-12/+12
execute.cc, entropy_source.h and v_ext_macros.h
2022-08-10Add #ifdef RISCV_ENABLE_COMMITLOG for commitlog related codeWeiwei Li1-0/+2
2022-06-01Remove the now-unused PC_SERIALIZE_WFIKip Walker1-1/+0
When WFI was changed to throw a C++ exception, the special-npc signaling became obsolete.
2022-05-19Move ebreak* logic from take_trap into instructions. (#1006)Tim Newsome1-0/+4
Now that logic only affects ebreak instructions, and does not affect triggers that also cause a trap to be taken. Fixes #725. Although like Paul, I don't have a test for this case. Introduce trap_debug_mode so so ebreak instructions can force entry into debug mode.
2022-05-04Fix the padding of register names in the log (#987)Shaked Flur1-1/+1
This fix print x5 as "x5 ", instead of "x 5".
2022-04-05Move trigger match logic into triggers.ccTim Newsome1-1/+1
2022-04-05trigger_matched_t -> triggers::matched_tTim Newsome1-1/+1
2022-03-30Replace state.mcontrol with TM.triggers.Tim Newsome1-1/+1
Created a new triggers::module_t to hold the structure. Also make sure mcontrol_t instances are properly initialized.
2022-03-30mcontrol_action_t -> triggers::action_tTim Newsome1-2/+2
These actions are not specific to the mcontrol trigger.
2022-02-19Make comment more germaneAndrew Waterman1-5/+1
2022-02-18Split out MINSTRET and MCYCLERupert Swarbrick1-0/+8
Before this change, the MCYCLE CSR was just a proxy for MINSTRET. Similarly, CYCLE was a proxy for INSTRET. This models a machine where every instruction takes exactly one cycle to execute. That's not quite precise enough if you want to do cosimulation: there, you're going to want to MCYCLE to actually match the behaviour of your processor (because you need reads from the relevant CSRs to give the expected result). This commit splits the two CSRs, leaving the other proxy relationships unchanged. The code in processor_t::step() which bumps MINSTRET now bumps MCYCLE by the same amount, maintaining the previous behaviour. Of course, now a cosimulation environment can update the value of MCYCLE to fix things up for multi-cycle instructions after they run.
2021-11-04Report proper GVA bit on breakpoint trapsScott Johnson1-1/+1
2021-11-04Add gva field to trap_breakpointScott Johnson1-1/+1
So I can fix breakpoints next to properly report gva.
2021-11-03Use appropriate subclass for breakpoint trapScott Johnson1-1/+1
Improves log because it now shows "trap_breakpoint" instead of "trap #3".
2021-09-29Convert vl to csr_tScott Johnson1-1/+1
Adds commit log events for vl to many vector instructions.
2021-09-26Convert dcsr to csr_tScott Johnson1-1/+1
2021-09-16Convert minstret to csr_tScott Johnson1-1/+1
This is a little messy in RV32 since it's accessed via two different CSRs (upper and lower halves). This changes logging of mcycle[h] to log a change to minstret[h], since that's how it's always been implemented in Spike. There is no separate mcycle register.
2021-07-28Inline execute_insnAndrew Waterman1-1/+1
2021-07-17commitlog: add toggle for wfiChih-Min Chao1-1/+3
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2021-06-02Remove Duff's Device in main simulation loop (#721)Andrew Waterman1-43/+12
With recent compilers on recent computers, the much simpler version of the code is actually slightly faster. I suspect, but haven't proven, that more accurate indirect jump prediction is the main explanation. Reduced I$ pressure might be a secondary factor.
2021-02-09Fix commit log for WFI instructionsAndrew Waterman1-0/+3
Resolves #642
2021-01-27Increment minstret when WFI completes (#636)Scott Johnson1-1/+1
See https://github.com/riscv/riscv-isa-manual/issues/189#issuecomment-768525017
2020-10-26commitlog: fix compilation warningChih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-10-06rvv: commitlog: get hartid directlyChih-Min Chao1-2/+1
To avoid handling inconsistent csr status when running with reference design Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-09-29Adding symbol lookup when --enable-commitlog is enabled (#558)sthiruva1-0/+5
* Adding symbol lookup when --enable-commitlog is enabled * Removed the #ifdef RISCV_ENABLE_COMMITLOG for all get_symbol related function Only retained the in processor.cc where it is called. Co-authored-by: Shajid Thiruvathodi <sthiruva@valtrix.in>
2020-09-28Add core id to lines generated by --log-commits (#556)sthiruva1-0/+4
* Add core id to lines generated by --log-commits * Fixing the format specifier for cpuid in log-commits Co-authored-by: Shajid Thiruvathodi <sthiruva@valtrix.in>
2020-07-08Extend trap classes to pass more informationAnup Patel1-1/+1
With hypervisor extension, we have more CSRs providing trap related information. We extend existing trap classes to pass additional trap information required by hypervisor extension. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2020-07-02commitlog: support csr accessChih-Min Chao1-1/+5
For csr register access instructions, there are log like Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-02commitlog: simplify print_value pathChih-Min Chao1-26/+27
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-02commitlog: extend hint bit to record csr accessChih-Min Chao1-2/+6
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-06-17rvv: commitlog: fix fractional lmul dumpChih-Min Chao1-2/+2
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-06-04rvv: fix compilation warningChih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-28rvv: extenc VU structure to support 0.9 new fieldsChih-Min Chao1-1/+5
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-26Report haltgroup halt cause, per the debug spec. (#473)Tim Newsome1-1/+3
2020-04-29rvv: commitlog: report status when memory trap occurs in vector load/storeChih-Min Chao1-6/+25
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-03-27Write execution logs to a named log file (#409)Rupert Swarbrick1-27/+37
This patch adds a --log argument to spike. If not given, the behaviour is unchanged: messages logging execution of instructions and (if commit logging is enabled) commits go to stderr. If --log=P is given, Spike now writes these messages to a log file at the path P. This is nice, because they are no longer tangled up with other errors and warnings. The code is mostly plumbing: passing a FILE* object through to the functions that were using stderr. I've written a simple "log_file_t" class, which opens a log file if necessary and yields it or stderr.
2020-03-23commitlog: fix wrong dump when exception occursChih-Min Chao1-7/+14
1. store_fault_access reorder the log and slow_path code 2. misaligned_access reset the log buffer in the beginning rather at the end of execution to avoid that uncompleted execution status is brought to the next instruction Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-03-09commitlog: enhance vector dumpChih-Min Chao1-5/+14
1. don't duplicate vconfig for lmul >=2 case 2. add l# to show prenset vl value Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-02-20commitlog: print vsew in bitChih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-02-18commitlog: fix printf format warningChih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-01-22commitlog: extend reg record to keep multiple accesssChih-Min Chao1-15/+55
1. use hash to keep duplicated register write since vector has lmul feature 2. enhance print fuction to support type larger than 64bit Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-01-13commitlog: extend load/store record to keep multiple accessChih-Min Chao1-7/+9
use vector to store memory accesses Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-12-16extend the commit and memory writes log feature with memory reads (#370)John Ingalls1-5/+11
2019-09-18Extends the commit log feature with memory writes. (#324)dave-estes-syzexion1-5/+14
* Extends the commit log feature with memory writes. This provides a little more information for debugging instruction traces, allowing you to maintain the state of memory as the trace is processed. The following sample trace output illustrates the formatting of the new memory writes. The first line is an instruction at location 0x80000094, containing the bytes (0x80830313) and commiting the value 0x80000898 to the register x6. The second line is an instruction which neither commits a register nor writes memory. The third line writes the value 0x0 to 0x80000890. 3 0x80000094 (0x80830313) x 6 0x80000898 3 0x80000098 (0x0062d663) 3 0x8000009c (0x00028023) mem 0x80000890 0x0 * Changes addressing feedback from review.
2019-09-18Adds --log-commits commandline option. (#323)dave-estes-syzexion1-1/+3
* Adds --log-commits commandline option. Similar to histogram support, the commit logging feature must be enabled with a configure option: --enable-commitlog. However, unlike that feature, there was no way to turn off the logging with a commandline option once the functionality was built in. This (git) commit provides that abilty. * Changes addressing review feedback.
2019-07-12Add debug_mode state bit, rather than overloading dcsr.causeAndrew Waterman1-3/+3
In the previous scheme, debug-mode software could exit debug mode by zeroing the dcsr.cause field. While benign, that behavior is out of spec.
2019-06-18rvv: extend interactive debugChih-Min Chao1-1/+0
add command to show vector register in debug mode Signed-off-by: Bruce Hoult <bruce@hoult.org>
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