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sifive/rvv0.9-phase2
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riscv
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encoding.h
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Author
Files
Lines
2020-04-14
rvv: add vfslide1[down|up].vf and refine checking rule
Chih-Min Chao
1
-0
/
+6
2020-04-14
rvv: add float conversion for rtz variants
Chih-Min Chao
1
-0
/
+18
2020-04-14
rvv: add new vcsr vector csr
Chih-Min Chao
1
-0
/
+2
2020-04-10
op: update CSR
Chih-Min Chao
1
-2
/
+28
2020-03-03
op: update encoding
Chih-Min Chao
1
-315
/
+372
2020-03-03
Add do-nothing support for mcountinhibit CSR
Rupert Swarbrick
1
-0
/
+2
2020-01-06
rvv : vmv[1248]r.v
Chih-Min Chao
1
-0
/
+12
2019-12-02
rvv: support new mstatus.vs field defined in v0.8
Chih-Min Chao
1
-0
/
+2
2019-11-27
rvv: replace vn suffic by 'w'
Chih-Min Chao
1
-36
/
+36
2019-11-27
rvv: add load/store whole register
Chih-Min Chao
1
-0
/
+6
2019-11-27
rvv: rename vfncvt suffix and add rod rouding type
Chih-Min Chao
1
-18
/
+18
2019-11-27
rvv: add quad insn and new vlenb csr
Chih-Min Chao
1
-21
/
+23
2019-11-17
Re-encode vaadd/vasub; remove vaadd.vi; add vaaddu/vasubu
Andrew Waterman
1
-43
/
+55
2019-10-22
rvv: remove vmford
Chih-Min Chao
1
-6
/
+0
2019-10-14
rvv: update encoding to v0.8
Chih-Min Chao
1
-12
/
+12
2019-09-05
rvv: change vext to vmv
Chih-Min Chao
1
-3
/
+3
2019-09-05
Revert "vext.x.v -> vmv.x.s; unary operation encoding changes"
Chih-Min Chao
1
-13
/
+13
2019-09-04
vext.x.v -> vmv.x.s; unary operation encoding changes
Andrew Waterman
1
-13
/
+13
2019-09-04
vmfirst/vmpopc have been renamed to vfirst/vpopc
Andrew Waterman
1
-32
/
+43
2019-06-13
rvv: separte vfunary0 into independent instructions
Chih-Min Chao
1
-3
/
+42
2019-06-13
rvv: spearate vfunary1 into independent instructions
Chih-Min Chao
1
-3
/
+6
2019-06-06
rvv: follow new instruction name change
Chih-Min Chao
1
-36
/
+30
2019-06-05
rvv: fix vmerge.vim/vmv.v.i encoding
Chih-Min Chao
1
-2
/
+2
2019-06-04
rvv: sepapate vfmerge
Chih-Min Chao
1
-3
/
+6
2019-06-04
rvv: move vadc/vsbc.v[vxi] to vadc/vsbc.v[vxi]m
Chih-Min Chao
1
-15
/
+30
2019-06-04
rvv: separate vmerge and vmv
Chih-Min Chao
1
-9
/
+18
2019-06-04
rvv: fix vs2 to v0
Chih-Min Chao
1
-2
/
+2
2019-06-04
rvv: vmiota_m -> viota_m
Chih-Min Chao
1
-3
/
+3
2019-06-04
rvv: change vseq.?? to vmseq.?? and related insns
Chih-Min Chao
1
-60
/
+60
2019-06-04
rvv: add vfrsub.vf
Chih-Min Chao
1
-0
/
+3
2019-06-04
rvv: add amo encoding
Chih-Min Chao
1
-0
/
+81
2019-06-04
rvv: change vfeq to vmfeq and related comparision instruction
Chih-Min Chao
1
-36
/
+36
2019-05-29
rvv: add fault-first load segment enconding
Chih-Min Chao
1
-7
/
+7
2019-05-20
rvv: change viota_m to vmiota_m
Chih-Min Chao
1
-3
/
+3
2019-05-19
rvv: separate vmuary0 by new encoding change
Chih-Min Chao
1
-21
/
+33
2019-05-16
rvv: fix integer reduction instruction suffix
Chih-Min Chao
1
-24
/
+24
2019-05-13
rvv: update encoding
Chih-Min Chao
1
-4
/
+32
2019-05-13
Revert "Add FLH and FSH instructions expanding IEEE fp16 in memory to fp32 in...
Chih-Min Chao
1
-6
/
+0
2019-04-24
rvv: fix sign-injection naming
Chih-Min Chao
1
-12
/
+12
2019-04-18
rvv: add CSR encoding
Dave.Wen
1
-0
/
+10
2019-04-02
rvv: fix encoding naming
Chih-Min Chao
1
-18
/
+18
2019-03-26
rvv: update decoding header for vector extension
Chih-Min Chao
1
-64
/
+915
2019-03-26
rvv: merge vssseg[3-6]w.v into vssw.v
Chih-Min Chao
1
-22
/
+1
2019-03-26
rvv: merge vlsseg[3-6]w.v into vlsw.v
Chih-Min Chao
1
-22
/
+1
2019-03-25
rvv: merge vsseg[3-6]w.v into vsw.v
Chih-Min Chao
1
-22
/
+1
2019-03-25
rvv: merge vlseg[3-6]w.v into vlw.v
Chih-Min Chao
1
-22
/
+1
2019-03-04
fix vmerge encoding -- int vv not fp vv
Bruce Hoult
1
-1
/
+1
2019-02-22
add encodings for instructions we need now, and more
Bruce Hoult
1
-6
/
+237
2019-02-21
fix vfmacc.vf encoding
Bruce Hoult
1
-1
/
+1
2019-02-13
Update to 20190131 spec
Bruce Hoult
1
-5
/
+5
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