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path: root/riscv/encoding.h
AgeCommit message (Expand)AuthorFilesLines
2019-11-15Re-encode vaadd/vasub; remove vaadd.vi; add vaaddu/vasubuAndrew Waterman1-43/+55
2019-10-29rvv: remove vmfordChih-Min Chao1-6/+0
2019-07-19vext.x.v -> vmv.x.s; unary operation encoding changesAndrew Waterman1-13/+13
2019-07-05vmfirst/vmpopc have been renamed to vfirst/vpopcAndrew Waterman1-32/+43
2019-06-14rvv: add the v-spec-0.7.1 encodingChih-Min Chao1-11/+1218
2017-11-27Rename badaddr to tvalAndrew Waterman1-4/+4
2017-11-27Rename sptbr to satpAndrew Waterman1-16/+16
2017-05-05UXL=SXL=MXLAndrew Waterman1-0/+3
2017-04-25FMV.X.S/FMV.S.X -> FMV.X.W/FMV.W.XAndrew Waterman1-6/+6
2017-04-25Remove hret instructionAndrew Waterman1-3/+0
2017-03-31update encoding.h to get PMP updatesYunsup Lee1-5/+6
2017-03-27Separate page faults from physical memory access exceptionsAndrew Waterman1-6/+12
2017-03-23Require little-endian hostAndrew Waterman1-0/+10
2017-03-22riscv: replace rtc device with a real clint implementationWesley W. Terpstra1-0/+2
2017-03-21riscv: remove dependency on num_coresWesley W. Terpstra1-3/+0
2017-03-20PUM -> SUM; expose MXR to S-modeAndrew Waterman1-2/+3
2017-03-16Simplify interrupt-stack disciplineAndrew Waterman1-0/+40
2017-03-13Implement mstatus.TW, mstatus.TVM, and mstatus.TSRAndrew Waterman1-0/+3
2017-02-26Sv57 and Sv64 are not spec'd yetAndrew Waterman1-14/+9
2017-02-25New counter enable schemeAndrew Waterman1-20/+8
2017-02-18Spike uarch needs TLB flush after SPTBR writeAndrew Waterman1-1/+0
2017-02-15sfence.vm -> sfence.vmaAndrew Waterman1-3/+3
2017-02-08Encode VM type in sptbr, not mstatusAndrew Waterman1-2/+118
2016-08-26Add (degenerate) performance counter facilityAndrew Waterman1-72/+341
2016-07-06Update to new PTE formatAndrew Waterman1-33/+10
2016-06-17Merge sasid into sptbrAndrew Waterman1-10/+15
2016-06-08Add degenerate HW breakpoint implementationAndrew Waterman1-0/+18
2016-06-03Keep DCSR_XDEBUGVER unsigned.Tim Newsome1-1/+1
2016-05-24New encoding.h for new CSR addresses.Tim Newsome1-4/+4
2016-05-23Change DCSR bits to match spec.Tim Newsome1-14/+14
2016-05-23Remove dependency on include file in my homedir.Tim Newsome1-0/+13
2016-05-23Software breakpoints sort of work.Tim Newsome1-0/+8
2016-05-23Remove unused code.Tim Newsome1-0/+2
2016-05-23Add dret.Tim Newsome1-0/+9
2016-05-22Allow delegation of device interruptsAndrew Waterman1-3/+6
2016-05-02Remove MIPI; mip.MSIP bit is read-onlyAndrew Waterman1-6/+0
2016-04-30Remove SCRs; add padding after config stringAndrew Waterman1-9/+11
2016-04-29Move much closer to new platform-M memory mapAndrew Waterman1-3/+6
2016-04-28Remove MTIME[CMP]; add RTC deviceAndrew Waterman1-8/+0
2016-04-19Split ERET into URET, SRET, HRET, MRETAndrew Waterman1-6/+15
2016-04-06Remove non-standard uarch CSRsAndrew Waterman1-40/+12
2016-03-03Fix up interrupt delegationAndrew Waterman1-2/+5
2016-03-02Add counter-enable registersAndrew Waterman1-0/+34
2016-03-02WIP on priv spec v1.9Andrew Waterman1-28/+16
2016-03-02New definitions of misa/marchid/mvendoridAndrew Waterman1-11/+13
2016-03-02implement PUM functionalityAndrew Waterman1-7/+8
2016-03-02Use simpler MTVEC schemeAndrew Waterman1-3/+5
2016-03-02WIP on priv spec v1.9Andrew Waterman1-51/+48
2015-11-12Generate device tree for target machineAndrew Waterman1-2/+76
2015-10-20Update to hopefully final RVC 1.9 encodingAndrew Waterman1-16/+10
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