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sifive/rvv0.9-phase2
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riscv
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encoding.h
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Author
Files
Lines
2020-06-16
zfh: op: add scalar opcode
Chih-Min Chao
1
-0
/
+108
2020-05-28
rvv: add new explicit eew load/store instructions
Chih-Min Chao
1
-134
/
+194
2020-05-28
rvv: add amo instructions
Chih-Min Chao
1
-54
/
+108
2020-05-28
rvv: add new singed/unsiged extension instructions
Chih-Min Chao
1
-0
/
+18
2020-05-28
rvv: op: change funary op
Chih-Min Chao
1
-47
/
+47
2020-05-26
Report haltgroup halt cause, per the debug spec. (#473)
Tim Newsome
1
-0
/
+1
2020-04-24
rvv: add vfslide1[down|up].vf and refine checking rule
Chih-Min Chao
1
-0
/
+6
2020-04-20
rvv: add float conversion for rtz variants
Chih-Min Chao
1
-0
/
+18
2020-04-20
Move vxrm/vxsat from fcsr to vcsr
Andrew Waterman
1
-0
/
+2
2020-04-09
op: update CSR
Chih-Min Chao
1
-2
/
+28
2020-03-09
op: rvv: update encoding
Chih-Min Chao
1
-315
/
+372
2020-02-28
Add do-nothing support for mcountinhibit CSR
Rupert Swarbrick
1
-0
/
+2
2020-01-13
rvv: add vmv[1248]r.v
Chih-Min Chao
1
-0
/
+12
2019-12-20
rvv: support new mstatus.vs field defined in v0.8
Chih-Min Chao
1
-0
/
+2
2019-12-20
rvv: replace vn suffic by 'w'
Chih-Min Chao
1
-36
/
+36
2019-12-20
rvv: add load/store whole register instructions
Chih-Min Chao
1
-0
/
+6
2019-12-20
rvv: rename vfncvt suffix and add rod rouding type
Chih-Min Chao
1
-18
/
+18
2019-12-20
rvv: add quad insn and new vlenb csr
Chih-Min Chao
1
-21
/
+23
2019-11-15
Re-encode vaadd/vasub; remove vaadd.vi; add vaaddu/vasubu
Andrew Waterman
1
-43
/
+55
2019-10-29
rvv: remove vmford
Chih-Min Chao
1
-6
/
+0
2019-07-19
vext.x.v -> vmv.x.s; unary operation encoding changes
Andrew Waterman
1
-13
/
+13
2019-07-05
vmfirst/vmpopc have been renamed to vfirst/vpopc
Andrew Waterman
1
-32
/
+43
2019-06-14
rvv: add the v-spec-0.7.1 encoding
Chih-Min Chao
1
-11
/
+1218
2017-11-27
Rename badaddr to tval
Andrew Waterman
1
-4
/
+4
2017-11-27
Rename sptbr to satp
Andrew Waterman
1
-16
/
+16
2017-05-05
UXL=SXL=MXL
Andrew Waterman
1
-0
/
+3
2017-04-25
FMV.X.S/FMV.S.X -> FMV.X.W/FMV.W.X
Andrew Waterman
1
-6
/
+6
2017-04-25
Remove hret instruction
Andrew Waterman
1
-3
/
+0
2017-03-31
update encoding.h to get PMP updates
Yunsup Lee
1
-5
/
+6
2017-03-27
Separate page faults from physical memory access exceptions
Andrew Waterman
1
-6
/
+12
2017-03-23
Require little-endian host
Andrew Waterman
1
-0
/
+10
2017-03-22
riscv: replace rtc device with a real clint implementation
Wesley W. Terpstra
1
-0
/
+2
2017-03-21
riscv: remove dependency on num_cores
Wesley W. Terpstra
1
-3
/
+0
2017-03-20
PUM -> SUM; expose MXR to S-mode
Andrew Waterman
1
-2
/
+3
2017-03-16
Simplify interrupt-stack discipline
Andrew Waterman
1
-0
/
+40
2017-03-13
Implement mstatus.TW, mstatus.TVM, and mstatus.TSR
Andrew Waterman
1
-0
/
+3
2017-02-26
Sv57 and Sv64 are not spec'd yet
Andrew Waterman
1
-14
/
+9
2017-02-25
New counter enable scheme
Andrew Waterman
1
-20
/
+8
2017-02-18
Spike uarch needs TLB flush after SPTBR write
Andrew Waterman
1
-1
/
+0
2017-02-15
sfence.vm -> sfence.vma
Andrew Waterman
1
-3
/
+3
2017-02-08
Encode VM type in sptbr, not mstatus
Andrew Waterman
1
-2
/
+118
2016-08-26
Add (degenerate) performance counter facility
Andrew Waterman
1
-72
/
+341
2016-07-06
Update to new PTE format
Andrew Waterman
1
-33
/
+10
2016-06-17
Merge sasid into sptbr
Andrew Waterman
1
-10
/
+15
2016-06-08
Add degenerate HW breakpoint implementation
Andrew Waterman
1
-0
/
+18
2016-06-03
Keep DCSR_XDEBUGVER unsigned.
Tim Newsome
1
-1
/
+1
2016-05-24
New encoding.h for new CSR addresses.
Tim Newsome
1
-4
/
+4
2016-05-23
Change DCSR bits to match spec.
Tim Newsome
1
-14
/
+14
2016-05-23
Remove dependency on include file in my homedir.
Tim Newsome
1
-0
/
+13
2016-05-23
Software breakpoints sort of work.
Tim Newsome
1
-0
/
+8
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