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AgeCommit message (Expand)AuthorFilesLines
2022-07-07update encoding.hWeiwei Li1-3381/+3444
2022-03-30Implement Sv57 and Sv57x4 translation modesAndrew Waterman1-0/+1
2022-01-19Fix HINVAL.VVMA and HINVAL.GVMA opcodesAndrew Waterman1-27/+204
2021-12-27Update instruction vmandnot.mm, vmornot.mm -> vmandn.mm, vmorn.mm (#896)Yueh-Ting (eop) Chen1-6/+6
2021-11-02Zbkx renames xperm.n and xperm.b as xperm4 and xperm8. (#846)Markku-Juhani O. Saarinen1-15/+15
2021-11-02Regenerate encoding.h from riscv-opcodes (#848)Scott Johnson1-22/+3
2021-09-27Allow `csrr mstatush` to see MPV and GVA bits tooScott Johnson1-0/+2
2021-09-08Move SSTATUS_VS_MASK into vsstatus_csr_tScott Johnson1-4/+0
2021-08-08Removed SWAP16 encoding and implementation header. (#766)marcfedorow1-3/+0
2021-07-30scalar-crypto: v0.9.4/arch-review entropy source updates.Ben Marshall1-10/+2
2021-07-28Update encoding.hAndrew Waterman1-146/+168
2021-07-28scalar-crypto: Remove DECLARE_RV*_ONLY macros from encoding.hBen Marshall1-21/+0
2021-07-28scalar-crypto: AES32 encoding changes post arch-reviewBen Marshall1-4/+4
2021-07-26Merge pull request #754 from chihminchao/clean-vqmac-vdotAndrew Waterman1-18/+0
2021-07-26decode: op: remove quad related macro and defineChih-Min Chao1-18/+0
2021-07-20Priv virtual memory updates (#750)Daniel Lustig1-0/+18
2021-06-07PTE N bit moved from bit 62 to bit 63 (#724)Daniel Lustig1-1/+1
2021-06-04scalar-crypto: Encoding fixes for v0.9.2Ben Marshall1-6/+6
2021-06-04encoding: udpate and move platform-related define outChih-Min Chao1-7/+1
2021-05-10Support RISC-V p-ext-proposal v0.9.2 (#637)ChunPing Chung1-0/+981
2021-03-08Merge pull request #649 from ben-marshall/scalar-crypto-fixAndrew Waterman1-12/+51
2021-02-24rvv: add vsetivliChih-Min Chao1-1/+4
2021-02-24rvv: add vse1/vle1Chih-Min Chao1-0/+6
2021-02-23rvv: rename sqrt/reciprocal instructionsChih-Min Chao1-7/+7
2021-02-18scalar-crypto: Fix decoding of RV64 AES instructions.Ben Marshall1-12/+51
2021-02-08Zsn has been renamed Svnapot (#641)Daniel Lustig1-1/+1
2021-01-22scalar-crypto: Initial spike support for v0.8.1 (#635)Ben Marshall1-0/+87
2021-01-17rvb: add xperm.[nbhw] (#629)Chih-Min Chao1-1/+13
2021-01-08Update Zba/Zbb/Zbc to v0.93; Zbs/Zbe to v0.94-draftAndrew Waterman1-378/+352
2020-12-02rvv: index load/store have benn separated into ordered and unordered parts (#...Chih-Min Chao1-72/+96
2020-11-23Fix VSSTATUS bits updation (#568)Anup Patel1-1/+1
2020-11-18Add Zsn extensionAndrew Waterman1-0/+1
2020-11-07Allow fixed endianness to be observed through MBE/SBE/UBEMarcus Comstedt1-1/+7
2020-10-22Swap MAX and MINU encodingsAndrew Waterman1-3/+3
2020-10-22[riscv-bitmanip] Add sh[123]add[u.w] instructionClifford Wolf1-0/+18
2020-10-22[riscv-bitmanip] Changes for RISC-V Bitmanip Spec 0.92Clifford Wolf1-8/+23
2020-10-22[riscv-bitmanip] Changes for RISC-V Bitmanip Spec 0.91Clifford Wolf1-25/+43
2020-10-22[riscv-bitmanip] Fix [un]shfl shamt lengthClifford Wolf1-2/+2
2020-10-22[riscv-bitmanip] Add bitmanip instructionsClifford Wolf1-0/+267
2020-08-31rvv: add reciprocal instructionsChih-Min Chao1-0/+6
2020-08-27rvv: remove quad instructionsChih-Min Chao1-12/+0
2020-08-04Merge pull request #521 from chihminchao/op-hypvervisorAndrew Waterman1-48/+48
2020-08-03op: hyperviosr: fix exception code and nameChih-Min Chao1-3/+3
2020-08-03op: rearrange hypbervisor op/csr/causeChih-Min Chao1-46/+46
2020-08-03op: rvv: fix pesudo code instructionsChih-Min Chao1-3/+3
2020-07-29rvv: add vrgatherei16.vvChih-Min Chao1-0/+3
2020-07-29rvv: add new whole reg load/store instructionsChih-Min Chao1-3/+69
2020-07-29rvv: op: rearrange some instruction since generation order changeChih-Min Chao1-36/+36
2020-07-29rvv: op: fix amo namingChih-Min Chao1-108/+108
2020-07-09Implement hypervisor CSRs read/writeAnup Patel1-3/+14