Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2017-11-27 | Rename badaddr to tval | Andrew Waterman | 1 | -4/+4 |
2017-11-27 | Rename sptbr to satp | Andrew Waterman | 1 | -16/+16 |
2017-05-05 | UXL=SXL=MXL | Andrew Waterman | 1 | -0/+3 |
2017-04-25 | FMV.X.S/FMV.S.X -> FMV.X.W/FMV.W.X | Andrew Waterman | 1 | -6/+6 |
2017-04-25 | Remove hret instruction | Andrew Waterman | 1 | -3/+0 |
2017-03-31 | update encoding.h to get PMP updates | Yunsup Lee | 1 | -5/+6 |
2017-03-27 | Separate page faults from physical memory access exceptions | Andrew Waterman | 1 | -6/+12 |
2017-03-23 | Require little-endian host | Andrew Waterman | 1 | -0/+10 |
2017-03-22 | riscv: replace rtc device with a real clint implementation | Wesley W. Terpstra | 1 | -0/+2 |
2017-03-21 | riscv: remove dependency on num_cores | Wesley W. Terpstra | 1 | -3/+0 |
2017-03-20 | PUM -> SUM; expose MXR to S-mode | Andrew Waterman | 1 | -2/+3 |
2017-03-16 | Simplify interrupt-stack discipline | Andrew Waterman | 1 | -0/+40 |
2017-03-13 | Implement mstatus.TW, mstatus.TVM, and mstatus.TSR | Andrew Waterman | 1 | -0/+3 |
2017-02-26 | Sv57 and Sv64 are not spec'd yet | Andrew Waterman | 1 | -14/+9 |
2017-02-25 | New counter enable scheme | Andrew Waterman | 1 | -20/+8 |
2017-02-18 | Spike uarch needs TLB flush after SPTBR write | Andrew Waterman | 1 | -1/+0 |
2017-02-15 | sfence.vm -> sfence.vma | Andrew Waterman | 1 | -3/+3 |
2017-02-08 | Encode VM type in sptbr, not mstatus | Andrew Waterman | 1 | -2/+118 |
2016-08-26 | Add (degenerate) performance counter facility | Andrew Waterman | 1 | -72/+341 |
2016-07-06 | Update to new PTE format | Andrew Waterman | 1 | -33/+10 |
2016-06-17 | Merge sasid into sptbr | Andrew Waterman | 1 | -10/+15 |
2016-06-08 | Add degenerate HW breakpoint implementation | Andrew Waterman | 1 | -0/+18 |
2016-06-03 | Keep DCSR_XDEBUGVER unsigned. | Tim Newsome | 1 | -1/+1 |
2016-05-24 | New encoding.h for new CSR addresses. | Tim Newsome | 1 | -4/+4 |
2016-05-23 | Change DCSR bits to match spec. | Tim Newsome | 1 | -14/+14 |
2016-05-23 | Remove dependency on include file in my homedir. | Tim Newsome | 1 | -0/+13 |
2016-05-23 | Software breakpoints sort of work. | Tim Newsome | 1 | -0/+8 |
2016-05-23 | Remove unused code. | Tim Newsome | 1 | -0/+2 |
2016-05-23 | Add dret. | Tim Newsome | 1 | -0/+9 |
2016-05-22 | Allow delegation of device interrupts | Andrew Waterman | 1 | -3/+6 |
2016-05-02 | Remove MIPI; mip.MSIP bit is read-only | Andrew Waterman | 1 | -6/+0 |
2016-04-30 | Remove SCRs; add padding after config string | Andrew Waterman | 1 | -9/+11 |
2016-04-29 | Move much closer to new platform-M memory map | Andrew Waterman | 1 | -3/+6 |
2016-04-28 | Remove MTIME[CMP]; add RTC device | Andrew Waterman | 1 | -8/+0 |
2016-04-19 | Split ERET into URET, SRET, HRET, MRET | Andrew Waterman | 1 | -6/+15 |
2016-04-06 | Remove non-standard uarch CSRs | Andrew Waterman | 1 | -40/+12 |
2016-03-03 | Fix up interrupt delegation | Andrew Waterman | 1 | -2/+5 |
2016-03-02 | Add counter-enable registers | Andrew Waterman | 1 | -0/+34 |
2016-03-02 | WIP on priv spec v1.9 | Andrew Waterman | 1 | -28/+16 |
2016-03-02 | New definitions of misa/marchid/mvendorid | Andrew Waterman | 1 | -11/+13 |
2016-03-02 | implement PUM functionality | Andrew Waterman | 1 | -7/+8 |
2016-03-02 | Use simpler MTVEC scheme | Andrew Waterman | 1 | -3/+5 |
2016-03-02 | WIP on priv spec v1.9 | Andrew Waterman | 1 | -51/+48 |
2015-11-12 | Generate device tree for target machine | Andrew Waterman | 1 | -2/+76 |
2015-10-20 | Update to hopefully final RVC 1.9 encoding | Andrew Waterman | 1 | -16/+10 |
2015-10-06 | RVC encoding tweak | Andrew Waterman | 1 | -29/+29 |
2015-10-05 | more work towards RVC 1.8 | Andrew Waterman | 1 | -41/+38 |
2015-10-02 | work towards rvc 1.8 | Andrew Waterman | 1 | -519/+552 |
2015-09-08 | Improve instruction fetch | Andrew Waterman | 1 | -0/+27 |
2015-09-04 | Move towards RVC v1.8 | Andrew Waterman | 1 | -38/+26 |