rocket-tools/riscv-gnu-toolchain/spike.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2020-05-19	rvv: fix widen checking	Chih-Min Chao	1	-4/+10
2020-05-19	rvv: store eew and emul to P.VU for unit/stride load/store	Chih-Min Chao	1	-22/+21
2020-05-18	rvv: fix unit/stride emul calculation	Chih-Min Chao	1	-3/+3
2020-05-18	rvv: fix compiler warning	Chih-Min Chao	1	-1/+1
2020-05-18	rvv: fix unit/strided load/store checking rule	Chih-Min Chao	1	-29/+18
2020-05-18	rvv: MLEN=1 overlapping	Dave.Wen	1	-4/+4
2020-05-17	rvv: mlen=1 WIP	Dave.Wen	1	-3/+4
2020-05-14	rvv: amo: only allow 32/64 bit element	Chih-Min Chao	1	-14/+1
2020-05-14	rvv: add vzext/vsext	Chih-Min Chao	1	-0/+32
2020-05-14	rvv: dont't explicit throw exception	Chih-Min Chao	1	-1/+1
2020-05-14	rvv: fix the fractional lmul	Dave.Wen	1	-1/+1
2020-05-13	rvv: wrong operation to the fractional LMUL bit	Dave.Wen	1	-1/+1
2020-05-13	rvv: change to 0.9amo	Chih-Min Chao	1	-2/+2
2020-05-13	rvv: amo pre-0.9	Chih-Min Chao	1	-0/+52
2020-05-13	rvv: fractional_lmul when lmul < 1	Dave.Wen	1	-4/+4
2020-05-13	vtype: fix the vta and vma functions and debugging display	Dave.Wen	1	-0/+3
2020-05-13	eew: add eew	Dave.Wen	1	-8/+17
2020-05-13	eew: fix the eew=0 case	Dave.Wen	1	-13/+16
2020-05-12	rvv: ldst: add missng check for VI_LD	Chih-Min Chao	1	-2/+1
2020-05-11	rvv: change to 0.9 ldst	Chih-Min Chao	1	-69/+83
2020-05-07	rvv: add eew and lmul for vle/vse/vleff	Dave.Wen	1	-2/+23
2020-04-27	rvv: align VCSR with upstream	Chih-Min Chao	1	-4/+4
2020-04-27	rvv: commitlog: fix comparision dst information	Chih-Min Chao	1	-4/+7
2020-04-24	rvv: commitlog: fix dst information for int comparison	Chih-Min Chao	1	-20/+40
2020-04-23	rvv: aad fp16 support for vfwxxx.[wv]v	Chih-Min Chao	1	-8/+20
2020-04-22	rvv: fix segment load/store nf checking	Chih-Min Chao	1	-5/+7
2020-04-21	rvv: fix floating comparison for fp16	Chih-Min Chao	1	-11/+22
2020-04-21	rvv: allow fp16	Chih-Min Chao	1	-1/+2
2020-04-15	rvv: add narrow conversion instrucitons	Chih-Min Chao	1	-0/+27
2020-04-15	rvv: add normal and widen reduction instructions	Chih-Min Chao	1	-15/+42
2020-04-15	rvv: add vmfxx f16 compare instructions	Chih-Min Chao	1	-2/+9
2020-04-15	rvv: add .vf fp16 instructions	Chih-Min Chao	1	-3/+9
2020-04-15	rvv: add .vv fp16 instructions	Chih-Min Chao	1	-2/+9
2020-04-15	rvv: WIDE_END loop macro	Chih-Min Chao	1	-9/+4
2020-04-15	fp16: add helper macro	Chih-Min Chao	1	-0/+8
2020-04-14	rvv: leave only SEW-bit segment store	Chih-Min Chao	1	-2/+2
2020-04-14	rvv: leave only sew-wise segment load	Chih-Min Chao	1	-8/+12
2020-04-14	rvv: add vfslide1[down\|up].vf and refine checking rule	Chih-Min Chao	1	-0/+9
2020-04-14	rvv: add new vcsr vector csr	Chih-Min Chao	1	-4/+4
2020-04-10	rvv: remove unecessary initialization	Chih-Min Chao	1	-1/+0
2020-04-10	rvv: fix index segment load overlapping check	Chih-Min Chao	1	-5/+7
2020-04-10	rvv: missing vector enabling check for mask operation	Chih-Min Chao	1	-0/+1
2020-03-23	rvv: restrict segment load register rule	Chih-Min Chao	1	-3/+1
2020-03-11	commitlog: fix missing dump for some instructions	Chih-Min Chao	1	-4/+4
2020-03-05	rvv: update the vector fredsum algorithm	Zhen Wei	1	-15/+23
2020-03-05	rvv: import parallel vf(w)redsum hardware impl.	Zhen Wei	1	-0/+53
2020-03-03	commitlog: fix conditional building error	Chih-Min Chao	1	-1/+3
2020-03-03	commitlog: enhance vector dump	Chih-Min Chao	1	-0/+1
2020-03-03	Debug can actually start at 0x0 now	Andrew Waterman	1	-2/+1
2020-03-03	rvv: vstart must be 0 for reduction instructions	Chih-Min Chao	1	-0/+1