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2019-07-22Writing non-existent CSRs, access FPRs with mstatus.FS=0 (#311)Tim Newsome2-9/+13
* Don't corrupt s0 when abstract CSR write fails. * Support abstract FPR access then mstatus.FS=0 Discussion on the spec list leans towards this being a requirement. Certainly users want their debugger to be able to access all registers regardless of target state.
2019-05-14Implement debug hasel support (#287)Tim Newsome2-10/+14
* Implement hasel/hawindow support. This should allow simultaneous resume and halt to work. * Fix anyrunning/anyhalted bits. * Add --without-hasel argument for testing. * Make halt/resume times more equal. Switching threads after every instruction executed in debug mode leads to a lot of extra instructions being executed on the "other" thread when both are really supposed to halt/resume near-simultaneously. Fixed that by adding wfi to debug_rom.S, and implementing it to switch to the other hart as well as check for JTAG input. When resuming, write the hart ID to the debug ROM so that the DM knows which hart actually resumed. (Before simultaneous resume it just assumed the current one.) Also got rid of resume symbol in debug_rom.S since it had no purpose. * Preserve Debug ROM entry points. * Make sure minstret is correct when wfi happens.
2018-03-06Fix install of a missed header from debug_rom.Prashanth Mundkur2-3/+3
The installed header files from the riscv subproject were incomplete, since processor.h includes debug_rom_defines.h, and the latter was not installed. Fix by moving it into riscv/, add it to the riscv subproject header list, which ensures it will get installed. While here, also add a missed dependency of debug_rom on riscv/encoding.h to debug_rom/Makefile.
2018-03-06Fix a missed header file in the softfloat include install.Prashanth Mundkur1-23/+0
2017-06-08`make clean && make` works again in debug_romTim Newsome2-2/+2
2017-04-18debug: Add fence and fence.i to ensure Debug RAM is ready.Megan Wachs2-26/+14
2017-04-18debug: Checkpoint which somewhat works with OpenOCD v13, but still has some ↵Megan Wachs1-0/+1
bugs.
2017-04-17debug: move the debug_rom defines to a seperate fileMegan Wachs2-5/+15
2017-04-17debug: Use more unique debug ROM namesMegan Wachs3-16/+32
2017-04-17debug: Use a more practical debug ROMMegan Wachs4-161/+83
2016-09-02Rebuild debug ROM because CSR encoding changed.Tim Newsome1-2/+2
2016-06-22Parameterize debug ROM contents on XLENAndrew Waterman4-28/+81
2016-06-22Remove fence.i from debug ROMAndrew Waterman1-1/+0
2016-06-09Fix 2 bugs in Debug ROM: (#52)Tim Newsome2-10/+12
1. Debug ROM wasn't actually writing 0xffffffff to the last word in Debug RAM after an exception happened. 2. Fix a race where debug interrupts were cleared before that write would have happened, so a debugger (gdbserver.cc in this case) might get the wrong idea about whether an exception happened or not. Why wasn't this wreaking havoc before?
2016-06-03DCSR cause was moved, bug debug ROM wasn't updatedTim Newsome2-3/+3
As a result Debug ROM would always take the spontaneous halt code path. This didn't hurt spike since (so far?) the spike debug handler doesn't attempt to do anything quick while code is running. But now the ROM is more correct.
2016-06-01Add gitignoreAndrew Waterman1-0/+2
2016-06-01Move sethaltnot and cleardebint.Tim Newsome2-4/+4
Now it matches Krste's memory map.
2016-05-24New encoding.h for new CSR addresses.Tim Newsome2-5/+5
2016-05-24Move cleardebint, per spec.Tim Newsome2-3/+3
2016-05-23Change DCSR bits to match spec.Tim Newsome2-22/+14
Cleaned up debug ROM code a little.
2016-05-23Move debug rom link map to the right place.Tim Newsome2-2/+2
Turns out this doesn't actually matter, but it's better to be correct.
2016-05-23Use fence.i in Debug ROM.Tim Newsome2-9/+10
This replaces a hack that just disabled all of the icache.
2016-05-23Add dret.Tim Newsome2-3/+2
2016-05-23Implement single memory read access.Tim Newsome2-24/+29
Prevent unaligned accesses in memory read. Also change how exceptions in Debug Mode are signaled.
2016-05-23Exceptions in Debug Mode, stay in Debug Mode.Tim Newsome2-16/+28
Now things don't blow up when reading a non-existent CSR.
2016-05-23Have Debug memory kind of working again.Tim Newsome2-14/+13
Debug exception -> ROM -> RAM -> ROM, then something goes wrong.
2016-05-23Fix race using fence.Tim Newsome2-21/+16
2016-05-23Refactor how we track in-progress operations.Tim Newsome1-0/+1
I think the functionality is unchanged.
2016-05-23processor_t unfriends gdbserver_t.Tim Newsome2-2/+2
2016-05-23Add debug_module bus device.Tim Newsome3-15/+14
This should replace the ROM hack I implemented earlier, but for now both exist together. Back to the point where gdb connects, core jumps to ROM->RAM->ROM.
2016-05-23ROM -> RAM -> ROM, waiting for debug int.Tim Newsome2-2/+2
2016-05-23Jump to the correct (temporary) Debug RAM address.Tim Newsome2-6/+7
2016-05-23Clean up how Debug ROM is included.Tim Newsome4-0/+154
I'm not thrilled about including a static copy in so many cc files, and making the compiler throw it out. But without really grokking the Makefile this is the best it's going to be.
2016-05-23Can jump to and execute Debug ROM.Tim Newsome4-154/+0
Connect with gdb, and the core will jump to Debug ROM and start executing it. Then it crashes when it jumps to 0x400 because Debug RAM isn't implemented (and doesn't live there anyway, for now).
2016-05-23Check in compiled debug ROM.Tim Newsome2-3/+24
Not everybody will have a cross-compiled toolchain set up when they build spike.
2016-05-23Add debug rom code.Tim Newsome3-0/+133
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