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2020-03-24add f16_classifyHan-Kuan Chen2-0/+37
2020-03-23rvv: restrict segment load register ruleChih-Min Chao4-3/+4
2020-03-23sf: simplify sNaN handling for fmax and fminChih-Min Chao1-24/+12
2020-03-23rvv: fix WARL behavior for vxsat and vxrmChih-Min Chao1-2/+2
2020-03-23use riscv-vector-tests ciHan-Kuan Chen1-22/+0
2020-03-17remove docker and use new pathHan-Kuan Chen3-23/+1
2020-03-17rvv: fix vdiv corner caseChih-Min Chao2-2/+2
2020-03-17rvv: sf: handle signaling NaN for fmax/fminChih-Min Chao1-2/+14
2020-03-16commitlog: fix build failedChih-Min Chao1-4/+6
2020-03-16commitlog: fix wrong dump when exception occurChih-Min Chao2-4/+9
2020-03-12rvv: commitlog: fix vrgather_vv dumpChih-Min Chao1-4/+4
2020-03-12rvv: fix vfmv.f.s and vfmv.s.fChih-Min Chao2-22/+21
2020-03-11commitlog: fix missing dump for some instructionsChih-Min Chao8-29/+32
2020-03-11rvv: respect vstart and vl for vfmv.s.fChih-Min Chao1-19/+22
2020-03-08Make debug printfs only show in debug builds. (#414)Andrew Waterman1-6/+6
2020-03-08Don't clobber trigger types when initializing stateAndrew Waterman1-1/+1
2020-03-05rvv: fix vf(w)redsum option parsing bugZhen Wei1-4/+5
2020-03-05rvv: avoid redundant std::string comparisonZhen Wei4-20/+40
2020-03-05rvv: update the vector fredsum algorithmZhen Wei1-15/+23
2020-03-05rvv: import parallel vf(w)redsum hardware impl.Zhen Wei7-16/+118
2020-03-03commitlog: fix conditional building errorChih-Min Chao1-1/+3
2020-03-03op: update encodingChih-Min Chao1-315/+372
2020-03-03commitlog: enhance vector dumpChih-Min Chao2-5/+15
2020-03-03rvv: handle middle value of vslidedown.vxChih-Min Chao1-1/+1
2020-03-03Add do-nothing support for mcountinhibit CSRRupert Swarbrick2-0/+3
2020-03-03Enable SOFTFLOAT_ROUND_ODD for vfncvt.rod.f.f.wAndrew Waterman1-0/+1
2020-03-03Check presence of [S|U] extension for mstatus.[sxl|uxl] read/writeUdit Khanna1-7/+8
2020-03-03Allow overriding CFLAGS and similar when buildingRupert Swarbrick6-24/+325
2020-03-03Allow debug accesses from MMUs not bound to processorsAndrew Waterman1-1/+1
2020-03-03Initialize some uninitialized stateAndrew Waterman2-1/+4
2020-03-03Disallow access to debug memory region unless in debug modeAndrew Waterman2-3/+31
2020-03-03Debug can actually start at 0x0 nowAndrew Waterman1-2/+1
2020-03-03rvv: vstart must be 0 for reduction instructionsChih-Min Chao1-0/+1
2020-03-04rvv: remove the option of vector misaligned accessZhen Wei10-46/+30
2020-03-04rvv: remove the option of vector impl. checkZhen Wei9-852/+3
2020-02-27use gitlab-eeHan-Kuan Chen1-92/+11
2020-02-26ci: change gdb versionChih-Min Chao1-1/+1
2020-02-27rvv: enable --varch to parse string type optionsZhen Wei3-34/+46
2020-02-20Revert "rvv modify the vfredsum.vs behavior with e27 xlen=32"Max Lin2-54/+9
2020-02-20rvv modify the vfredsum.vs behavior with e27 xlen=32Max Lin2-9/+54
2020-02-20rvv: only check segment overlapping in index loadChih-Min Chao1-4/+2
2020-02-19rvv: also relax vmerge_vim/vvm when lmul = 1Chih-Min Chao2-2/+0
2020-02-19rvv: also relax lmul in vfwredumChih-Min Chao2-2/+0
2020-02-19commitlog: print vsew in bitChih-Min Chao1-1/+1
2020-02-19rvv: don't zero vstart in the beginningChih-Min Chao1-1/+0
2020-02-19Vector stores don't care if rd overlaps v0 (#400)Andrew Waterman5-13/+20
2020-02-19widening reductions are legal when LMUL=8Andrew Waterman1-1/+0
2020-02-19v[f]merge: allow v0 overlap if LMUL = 1Andrew Waterman2-2/+0
2020-02-19vadc/vsbc: allow v0 overlap if LMUL = 1Andrew Waterman1-2/+2
2020-02-19Make CLINT API use Hz instead of MHzAndrew Waterman3-6/+6
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