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2020-09-22Only install pkg-config files for libraries that are installedAndrew Waterman9-91/+1
Resolves #549
2020-09-22Separate build of spike and spike-dasmAndrew Waterman14-4/+121
2020-09-22Don't error out if dlopen isn't availableAndrew Waterman3-13/+27
2020-09-21Raise virtual-instruction traps correctly for WFI/SRET/SFENCEAndrew Waterman3-4/+6
2020-09-20Fix polarity of hstatus.HU fieldAndrew Waterman13-13/+13
2020-09-20Don't throw virtual instruction exceptions for unimplemented CSRsAndrew Waterman9-115/+133
2020-09-15rvv: fix int type is not enough to do shift (#544)Han-Kuan Chen2-2/+2
int can only represent 32 bit in lp64 model when sew is greater than 32, the behavior is undefined
2020-09-15Populate tval registers on illegal-/virtual-instruction trapsAndrew Waterman9-20/+26
2020-09-15No need to catch illegal CSRs in set_csrAndrew Waterman1-16/+2
get_csr is always called first (and this assumption is pervasively relied upon), so the checks in set_csr are redundant. FYI @avpatel
2020-09-11Add MIP_MEIP to all_ints (#543)Abhinay Kayastha1-1/+1
2020-09-08Merge pull request #542 from chihminchao/rvv-fix-2020-09-08Andrew Waterman1-15/+45
Rvv fix 2020 09 08
2020-09-08rvv: disasm: separate vvm and vvChih-Min Chao1-14/+44
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-09-08rvv: disasm: fix vamoadd nameChih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-09-01Fix MIDELEG and MEDELEG emulation when H-extension is available (#537)Anup Patel1-0/+7
This patch does two fixes when H-extension is available: 1. The MEDELEG should allow delegating VIRTUAL_SUPERVISOR_ECALL instead of SUPERVISOR_ECALL. This was broken after commit 7775c6fb7cc1b. 2. The forced bits in MIDELEG should be cleared when 'H' bit is cleared in MISA CSR. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2020-08-31Merge pull request #535 from chihminchao/rvv-pre-1.0-2020-08-27Andrew Waterman38-109/+525
Rvv pre 1.0 2020 08 27
2020-08-31rvv: reading vcsr needs to enable mstatus.vsChih-Min Chao1-0/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-08-31rvv: disasm: fix amo sub-opcodeChih-Min Chao1-5/+4
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-08-31rvv: disasm: fix whole loadChih-Min Chao1-3/+10
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-08-31rvv: relax checking for vs1Chih-Min Chao3-2/+31
vs1 is sub-op Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-08-31rvv: trigger exp for illegal ncvt/wcvt eewChih-Min Chao16-26/+26
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-08-31rvv: check invalid frm for floating operationsChih-Min Chao3-0/+4
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-08-31rvv: add reciprocal instructionsChih-Min Chao5-0/+32
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-08-31softfloat: add reciprocal apiChih-Min Chao3-0/+399
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-08-27rf: remove bit extraction from processor.hChih-Min Chao3-9/+18
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-08-27rvv: remove quad instructionsChih-Min Chao12-64/+0
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-08-20Fix debug tests failing with impebreak enabled. (#530)Tim Newsome1-1/+1
Introduced in #527.
2020-08-20Merge pull request #533 from chihminchao/rvv-fix-2020-08-20Andrew Waterman1-1/+2
rvv: fix vrgatherei16 overlap rule
2020-08-20rvv: fix vrgatherei16 overlap ruleChih-Min Chao1-1/+2
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-08-12mcounteren does not exist if U-mode is not implementedAndrew Waterman1-1/+4
2020-08-11Merge pull request #527 from sobuch/optional-impebreakAndrew Waterman3-7/+15
Add option to dissable implicit ebreak in program buffer
2020-08-11Add option to dissable implicit ebreak in program bufferSamuel Obuch3-7/+15
2020-08-04Merge pull request #521 from chihminchao/op-hypvervisorAndrew Waterman3-51/+51
Op hypvervisor
2020-08-04Merge pull request #520 from chihminchao/rvv-enhance-vstartAndrew Waterman24-39/+48
Rvv enhance vstart
2020-08-03op: hyperviosr: fix exception code and nameChih-Min Chao3-6/+6
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-08-03op: rearrange hypbervisor op/csr/causeChih-Min Chao1-46/+46
The change comes from the generation order in riscv-opcodes. The original definition is placed in opcode-system but the new one is placed in separated opcode-rv64h and opcode-rv32h. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-08-03rvv: add 'vstartalu" option to --varch arugmentChih-Min Chao23-36/+45
except for load/store instructions 0 : all instruction can't have non-zero vstart not 0 : all instruction can have non-zero vstart if it is not required vstart must be zero in spec the default value is 1 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-08-03op: rvv: fix pesudo code instructionsChih-Min Chao1-3/+3
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-30Merge pull request #519 from chihminchao/rvv-pre-1.0Andrew Waterman64-282/+483
Rvv pre 1.0
2020-07-29f16: fix Nan-Box macroChih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-29rvv: fix frac_lmul get functionChih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-29rvv: remove isa string zvamoand zvlssegChih-Min Chao3-18/+0
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-29rvv: remove veew/vemul stateChih-Min Chao3-32/+25
They aren't arch state Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-29rvv: add vrgatherei16.vvChih-Min Chao4-13/+51
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-29rvv: add new whole reg load/store instructionsChih-Min Chao25-23/+212
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-29rvv: op: rearrange some instruction since generation order changeChih-Min Chao1-36/+36
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-29rvv: op: fix amo namingChih-Min Chao39-148/+148
The original name misses the 'i' in instruction mae vamoswape8 -> vamoswapei8 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-29rvv: remove slenChih-Min Chao2-8/+5
The command parser still can accept SLEN but the value is not stored in implementation Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-29rvv: initialize vector register as zeroChih-Min Chao1-1/+2
some dump and comparison tool may depennd the initial state of vector register. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-29rvv: disasm: fix missing vamoorei operandsChih-Min Chao1-1/+2
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-28Merge pull request #517 from riscv/rvv-1.0-vtypeAndrew Waterman2-5/+4
Incorporate RVV 1.0 vtype layout change
generated by cgit v1.1 at 2024-07-11 12:19:18 +0000