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2020-10-15reduce sig_len constraint to 4 bytes (#569)Neel Gala2-6/+20
* reduce sig_len constraint to 4 bytes Spike currently asserts that the signature length should always be a multiple of 16-bytes. However, the compliance suite has agreed to upon the signature being a multiple ot 4-bytes. This prevents some of the tests to run on spike since it fails the assertion. The proposed change fixes this issue and reduces the assertion to 4 bytes. * Added size argument to htif arguments and zero padding for signature output. Defaultline size-16. * Modified type of line_size to unsigned. * Renamed size to granularity. * Rename granularity to signature-granularity. Co-authored-by: dracarys99 <spawan1999@gmail.com>
2020-10-10Fix new ELF checks on big endian hosts (#567)Marcus Comstedt1-4/+6
The new macros IS_ELF_... introduced in 80b5b2f5 were not endian safe.
2020-10-08Raise correct exception for counters when V=1Andrew Waterman1-21/+18
Resolves #566
2020-10-06Merge pull request #565 from chihminchao/rvv-fix-2020-10-06Andrew Waterman4-4/+3
Rvv fix 2020 10 06
2020-10-06rvv: remove elen >= max(xlen, flen) checkChih-Min Chao1-2/+0
The original constraint is for baseline u-arch but could be more flexsible Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-10-06rvv: commitlog: get hartid directlyChih-Min Chao2-2/+2
To avoid handling inconsistent csr status when running with reference design Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-10-06rvv: vamo needs to keep exception index in vstartChih-Min Chao1-0/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-10-06rvv: sstatus.SD needs to include vs dirty state (#563)Chih-Min Chao1-1/+2
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-10-06Update SATP and HGATP mask usage to make it clearer (#564)Abhinay Kayastha1-3/+3
2020-10-05Fix Mac OS buildAndrew Waterman1-0/+1
2020-10-04It should never be possible to select MPP=2Andrew Waterman1-1/+1
This completes the fix in 8d860c190640e19e0f23a21d2479b4a36d13d342 to cover the hypervisor extension case as well. Fixes #557
2020-10-01decode: only return meaningful bits for insn_t (#561)Chih-Min Chao1-1/+1
The original insn_t has the upper part with extended signed bit when the instruction is fetched from mmu_t::refill_icache. It makes the tval of illegal instruction exception wrong. ref: As the spec 3.1.17 says, after an illegal instruction trap, mtval will contain the shortest of: 1. the actual faulting instruction 2. the first ILEN bits of the faulting instruction 3. the first XLEN bits of the faulting instruction The value loaded into mtval is right-justified and all unused upper bits are cleared to zero. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-09-29Partially revert removal of .pc.in files; add disasm.pc.inAbhinay Kayastha4-1/+18
2020-09-29Adding symbol lookup when --enable-commitlog is enabled (#558)sthiruva8-0/+50
* Adding symbol lookup when --enable-commitlog is enabled * Removed the #ifdef RISCV_ENABLE_COMMITLOG for all get_symbol related function Only retained the in processor.cc where it is called. Co-authored-by: Shajid Thiruvathodi <sthiruva@valtrix.in>
2020-09-28Add core id to lines generated by --log-commits (#556)sthiruva1-0/+4
* Add core id to lines generated by --log-commits * Fixing the format specifier for cpuid in log-commits Co-authored-by: Shajid Thiruvathodi <sthiruva@valtrix.in>
2020-09-24pmp: fix local scope issue (#552)Chih-Min Chao1-3/+3
There is an global 'res' in function and local 'res' in pmpcfg loop. This makes the 'ret' macro use the local res but what we want is to pass local result to global 'res' Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-09-24correctly respect mstatus.TW and hstatus.VTWAndrew Waterman1-2/+9
2020-09-24Correctly respect mstatus.TSRAndrew Waterman1-3/+6
It never has effect when V=1.
2020-09-24Correctly respect mstatus.TVMAndrew Waterman3-7/+14
It never has effect when V=1. HFENCE.GVMA and the hgatp CSR must respect it (when V=0).
2020-09-24Fix priority of virtual vs. illegal instruction exceptions for HFENCEAndrew Waterman2-2/+2
2020-09-24Fix priority of virtual vs. illegal instruction exceptions for HLV/HSVAndrew Waterman13-13/+13
Resolves #551
2020-09-23Merge pull request #550 from chihminchao/rvv-pre-1.0-2020-09-22Andrew Waterman18-19/+178
Rvv pre 1.0 2020 09 22
2020-09-23rvv: commitlog: add peek parameter to get_csrChih-Min Chao2-3/+7
commitlog needs to read all affected csrs but some of them may violate the permisson. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-09-22rvv: fix vfncvt/vfwcvt type checkingChih-Min Chao16-16/+171
for each case, use explicit type checking Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-09-22Add basic continuous-integration flowAndrew Waterman3-0/+41
2020-09-22Only install pkg-config files for libraries that are installedAndrew Waterman9-91/+1
Resolves #549
2020-09-22Separate build of spike and spike-dasmAndrew Waterman14-4/+121
2020-09-22Don't error out if dlopen isn't availableAndrew Waterman3-13/+27
2020-09-21Raise virtual-instruction traps correctly for WFI/SRET/SFENCEAndrew Waterman3-4/+6
2020-09-20Fix polarity of hstatus.HU fieldAndrew Waterman13-13/+13
2020-09-20Don't throw virtual instruction exceptions for unimplemented CSRsAndrew Waterman9-115/+133
2020-09-15rvv: fix int type is not enough to do shift (#544)Han-Kuan Chen2-2/+2
int can only represent 32 bit in lp64 model when sew is greater than 32, the behavior is undefined
2020-09-15Populate tval registers on illegal-/virtual-instruction trapsAndrew Waterman9-20/+26
2020-09-15No need to catch illegal CSRs in set_csrAndrew Waterman1-16/+2
get_csr is always called first (and this assumption is pervasively relied upon), so the checks in set_csr are redundant. FYI @avpatel
2020-09-11Add MIP_MEIP to all_ints (#543)Abhinay Kayastha1-1/+1
2020-09-08Merge pull request #542 from chihminchao/rvv-fix-2020-09-08Andrew Waterman1-15/+45
Rvv fix 2020 09 08
2020-09-08rvv: disasm: separate vvm and vvChih-Min Chao1-14/+44
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-09-08rvv: disasm: fix vamoadd nameChih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-09-01Fix MIDELEG and MEDELEG emulation when H-extension is available (#537)Anup Patel1-0/+7
This patch does two fixes when H-extension is available: 1. The MEDELEG should allow delegating VIRTUAL_SUPERVISOR_ECALL instead of SUPERVISOR_ECALL. This was broken after commit 7775c6fb7cc1b. 2. The forced bits in MIDELEG should be cleared when 'H' bit is cleared in MISA CSR. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2020-08-31Merge pull request #535 from chihminchao/rvv-pre-1.0-2020-08-27Andrew Waterman38-109/+525
Rvv pre 1.0 2020 08 27
2020-08-31rvv: reading vcsr needs to enable mstatus.vsChih-Min Chao1-0/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-08-31rvv: disasm: fix amo sub-opcodeChih-Min Chao1-5/+4
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-08-31rvv: disasm: fix whole loadChih-Min Chao1-3/+10
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-08-31rvv: relax checking for vs1Chih-Min Chao3-2/+31
vs1 is sub-op Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-08-31rvv: trigger exp for illegal ncvt/wcvt eewChih-Min Chao16-26/+26
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-08-31rvv: check invalid frm for floating operationsChih-Min Chao3-0/+4
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-08-31rvv: add reciprocal instructionsChih-Min Chao5-0/+32
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-08-31softfloat: add reciprocal apiChih-Min Chao3-0/+399
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-08-27rf: remove bit extraction from processor.hChih-Min Chao3-9/+18
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-08-27rvv: remove quad instructionsChih-Min Chao12-64/+0
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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