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AgeCommit message (Expand)AuthorFilesLines
2018-04-30Debug ROM: Adjust debug ROM to have fewer icache flushestweak_debug_romMegan Wachs1-13/+12
2018-04-29When no arguments are passed, print spike help, not fesvr helpAndrew Waterman1-3/+3
2018-04-04Allow querying the mmu configuration chosen during the build. (#191)Prashanth Mundkur1-0/+18
2018-04-04Revert "Fix for issue #183: No illegal instruction exception for c.sxxi instr...Andrew Waterman3-3/+3
2018-03-30Merge pull request #189 from pmundkur/pm-csr-name-apiPalmer Dabbelt2-0/+10
2018-03-26Add an api to get the name for a CSR.Prashanth Mundkur2-0/+10
2018-03-21Implement Hauser misa.C misalignment proposal (#187)Andrew Waterman4-6/+12
2018-03-21Fix the access exception during page-table walks to match the original access...Prashanth Mundkur1-1/+9
2018-03-19Fix spike-dasm. (#184)Tim Newsome1-1/+2
2018-03-19Merge pull request #182 from riscv/reset_bitsTim Newsome5-1/+33
2018-03-16Implement debug havereset bitsTim Newsome5-1/+33
2018-03-16Merge branch 'deepsrc-b_fix_issue183'Andrew Waterman19-59/+117
2018-03-16Fix for issue #183: No illegal instruction exception for c.sxxi instructions ...Shubhodeep Roy Choudhury3-3/+3
2018-03-14Fix a bug caused by moving misa into state_t. (#180)Prashanth Mundkur2-3/+4
2018-03-13Move processor.isa to state.misa, since it really belongs there.Prashanth Mundkur2-10/+10
2018-03-09Fix single stepping csrrw instructions (#178)Tim Newsome1-8/+7
2018-03-07Merge pull request #177 from riscv/debug_authTim Newsome6-13/+59
2018-03-06Narrow the interface used by the processors and memory to the top-level simul...Prashanth Mundkur8-17/+28
2018-03-06Fix install of a missed header from debug_rom.Prashanth Mundkur4-5/+5
2018-03-06Fix a missed header file in the softfloat include install.Prashanth Mundkur2-0/+1
2018-03-03Implement clearing-misa.C-while-PC-is-misaligned proposalAndrew Waterman9-3/+15
2018-03-03Enforce 2-byte alignment of mepc/sepc/dpcAndrew Waterman1-3/+3
2018-03-01Merge pull request #173 from riscv/no_progbuf3Tim Newsome2-35/+98
2018-02-27Add debug module authentication.Tim Newsome6-13/+59
2018-02-21Don't allow 32-bit instructions to take up multiple slots in I$Andrew Waterman2-17/+4
2018-02-19Merge pull request #171 from riscv/sysbusbitsTim Newsome6-91/+299
2018-02-19Passes smoke tests with --progsize=0Tim Newsome1-15/+82
2018-02-19WIP. Doesn't work.Tim Newsome2-40/+36
2018-02-13Implement cycleh/instreth CSRs for RV32 (#172)Andrew Waterman1-0/+5
2018-02-01Add --debug-sba optionTim Newsome5-52/+50
2018-01-29Update debug_definesTim Newsome3-53/+53
2018-01-18Support debug system bus access.Tim Newsome5-20/+230
2018-01-09Use new debug_defines.h.Tim Newsome1-19/+19
2018-01-08mem_t: Throw an error if zero-sized memory is requested (#168)Jonathan Neuschäfer2-0/+4
2018-01-03Add some missing RVC instructions to disassemblerAndrew Waterman1-0/+3
2017-12-18Merge pull request #165 from riscv/small_progbufTim Newsome7-484/+487
2017-12-11Update debug_defines to latest version.Tim Newsome1-22/+48
2017-12-11Set impebreak.Tim Newsome2-1/+9
2017-12-11Update to latest debug_defines.h.Tim Newsome3-465/+411
2017-12-11Make progbuf a run-time option.Tim Newsome6-19/+42
2017-11-27Rename badaddr to tvalAndrew Waterman5-25/+25
2017-11-27Rename sptbr to satpAndrew Waterman5-36/+36
2017-11-27Set tval to 0 on traps with no specified tvalAndrew Waterman2-5/+3
2017-11-20Implement priv-1.11 interrupt-priority scheme (#161)Andrew Waterman1-1/+18
2017-11-20Fix commitlog. (#162)Christopher Celio1-5/+8
2017-11-15Merge pull request #156 from p12nGH/noncontiguous_hartsAndrew Waterman3-5/+31
2017-11-15hartids knob description addedGleb Gagarin1-0/+1
2017-11-15Support for non-contiguous hartidsGleb Gagarin3-5/+30
2017-11-09Remove redundant U/S mode advertisementAndrew Waterman1-4/+0
2017-11-09H-mode no longer existsAndrew Waterman2-2/+0
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