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AgeCommit message (Expand)AuthorFilesLines
2019-11-21Allow delegating misaligned load/store, illegal instructionpte-info-and-delegationUdit Khanna1-0/+3
2019-11-21Print page fault informationUdit Khanna1-1/+7
2019-09-27Fixed match trigger MATCH_NAPOT case. (#335)fborisovskii1-1/+1
2019-09-18Extends the commit log feature with memory writes. (#324)dave-estes-syzexion3-6/+37
2019-09-18Adds --log-commits commandline option. (#323)dave-estes-syzexion6-2/+34
2019-09-05Fix formatting in READMEAndrew Waterman1-1/+1
2019-09-02Fix OSX buildAndrew Waterman3-2/+131
2019-08-28Merge pull request #315 from vexingcodes/mmio-pluginAndrew Waterman9-7/+225
2019-08-23Fix c.fldsp/c.fsdsp disassembly bugAndrew Waterman1-2/+2
2019-08-23Remove statement with no effectAndrew Waterman1-1/+0
2019-07-22Implement MMIO device plugins.Aaron Jones9-7/+225
2019-07-19Set vtype.vill correctly; also reset it to trueAndrew Waterman1-3/+8
2019-07-19Check presence of V extension when accessing vector CSRsAndrew Waterman1-0/+15
2019-07-19Check vtype.vill for all vector instructions except vsetvl[i]Andrew Waterman24-20/+37
2019-07-19VL and VTYPE aren't writable CSRsAndrew Waterman1-12/+0
2019-07-19Check for F extension in vfmv instructionsAndrew Waterman2-0/+2
2019-07-19Avoid relying on sizeof longAndrew Waterman3-5/+5
2019-07-19Link with libsoftfloat.a (but still build libsoftfloat.so)Andrew Waterman1-4/+4
2019-07-19vext.x.v -> vmv.x.s; unary operation encoding changesAndrew Waterman5-45/+40
2019-07-16Writing non-existent CSRs, access FPRs with mstatus.FS=0 (#311)Tim Newsome7-16/+60
2019-07-12Merge pull request #309 from riscv/dretAndrew Waterman5-12/+15
2019-07-12Remove old header from makefileAndrew Waterman1-1/+0
2019-07-12DRET should not be legal in M-modeAndrew Waterman1-1/+1
2019-07-12Add debug_mode state bit, rather than overloading dcsr.causeAndrew Waterman5-11/+14
2019-07-11Update READMEAndrew Waterman1-1/+1
2019-07-11Fix support for 32-bit hosts (but no V extension in that case!)Andrew Waterman6-6/+14
2019-07-11Fix some 32-bit safety issuesAndrew Waterman2-3/+3
2019-07-11ChangeLog formattingAndrew Waterman1-1/+1
2019-07-11Update ChangeLogAndrew Waterman1-8/+10
2019-07-11Support S-mode vectored interruptsAndrew Waterman2-2/+4
2019-07-05vmfirst/vmpopc have been renamed to vfirst/vpopcAndrew Waterman5-36/+47
2019-07-05Avoid static initializers for variable-length arraysAndrew Waterman1-2/+2
2019-07-05Add override modifier to fix clang warningsAndrew Waterman1-2/+2
2019-07-05Fix clang uninitialized variable warningAndrew Waterman1-1/+1
2019-06-18Merge pull request #303 from chihminchao/rvv-0.7.1-rc2Andrew Waterman371-1675/+7544
2019-06-18rvv: describe the supported vector spec versionChih-Min Chao1-0/+1
2019-06-18rvv: add simple instruction parsing toolChih-Min Chao3-1/+70
2019-06-18rvv: add floating-point instructionsChih-Min Chao83-1/+869
2019-06-18rvv: add load/store instructionsChih-Min Chao46-0/+569
2019-06-18rvv: add integer/fixed-point/mask/reduction/permutation instructionsChih-Min Chao217-0/+3473
2019-06-18rvv: add control instructions and system register accessChih-Min Chao5-0/+42
2019-06-18rvv: add saturation helper functionChih-Min Chao3-44/+112
2019-06-18rvv: extend softfloat to support 16-64 min/max functionChih-Min Chao3-0/+88
2019-06-18rvv: extend interactive debugChih-Min Chao3-1/+51
2019-06-14rvv: add varch option parser and initialize vector unitChih-Min Chao6-13/+78
2019-06-14rvv: add vector unit structureChih-Min Chao2-0/+144
2019-06-14rvv: add configuration and command-line optionChih-Min Chao5-0/+107
2019-06-14rvv: disasm: add v-spec 0.7.1 supportChih-Min Chao4-3/+556
2019-06-14disams: make instruction name dynamicChih-Min Chao1-1/+2
2019-06-14rvv: add the v-spec-0.7.1 encodingChih-Min Chao2-1482/+1218
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