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-rw-r--r--riscv/simif.h11
1 files changed, 11 insertions, 0 deletions
diff --git a/riscv/simif.h b/riscv/simif.h
index 1d982b3..5834a87 100644
--- a/riscv/simif.h
+++ b/riscv/simif.h
@@ -4,6 +4,13 @@
#define _RISCV_SIMIF_H
#include "decode.h"
+#include <map>
+
+// LR/SC
+struct reservation {
+ uint32_t id;
+ bool valid;
+};
// this is the interface to the simulator used by the processors and memory
class simif_t
@@ -16,6 +23,10 @@ public:
virtual bool mmio_store(reg_t addr, size_t len, const uint8_t* bytes) = 0;
// Callback for processors to let the simulation know they were reset.
virtual void proc_reset(unsigned id) = 0;
+
+ // get the LR/SC's reservation set
+ virtual std::map<reg_t, reservation>& get_reservation_set() = 0;
+ virtual reg_t get_reservation_set_size() = 0;
};
#endif