diff options
Diffstat (limited to 'riscv/execute.cc')
-rw-r--r-- | riscv/execute.cc | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/riscv/execute.cc b/riscv/execute.cc index 3f7584e..41a15b7 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -349,6 +349,14 @@ void processor_t::step(size_t n) } state.minstret->bump(instret); + + // By default, bump the MCYCLE register by the same delta. This models a + // machine where each instruction takes exactly one cycle to retire. In a + // cosimulation environment, the RTL might manually update MCYCLE + // separately. It should do that between the end of this step() and the + // start of the next one. + state.mcycle->bump(instret); + n -= instret; } } |